Field-Programmable Gate Arrays

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XMatchPRO algorithm on FPGA

Hi there, has anyone ever tried to implement the XMatch-Pro lossless data compression algorithm on an FPGA and finally...
0 comments posted 20yrs
posted by delbarestivale
0 comments posted 20yrs posted by delbarestivale

IIR FPGA 'crosspost'

Hi, I have posted on comp.dsp about this and got interesting answers. I have just discovered this group so I would like...
1 comments posted 20yrs
posted by stephaneo
1 comments posted 20yrs posted by stephaneo

PLL clock in in Stratix

hello, I would like to use the PLL with a clock frequency below 4 MHz. But when I use the MegaFunction under Quartus, i...
0 comments posted 20yrs
posted by patrick.melet
0 comments posted 20yrs posted by patrick.melet

Départs en vacances et distances de sécurité

Vendredi dernier (14 juillet), vers 10 h, la radio d'autoroute locale indiquait que la circulation sur l'autoroute A7 e...
2 comments posted 20yrs
posted by anonymous
2 comments posted 20yrs posted by anonymous

Linux on an XUP board - cant access user IP!

Hey all, I'm currently bringing up Linux on a Xilinx XUP demo board and I could use some assistance. For those who are...
0 comments posted 20yrs
posted by scotto2hot-list
0 comments posted 20yrs posted by scotto2hot-list

Using DCM-Virtex-II Pro

Hi, I using Xilinx System Generator tool and need to use DCM for Virtex-II Pro board. But after searching on internet I...
2 comments posted 20yrs
posted by junaidabidi
2 comments posted 20yrs posted by junaidabidi

Creating EDIF from Verilog, then using VHDL wrapper

Hi group, here's a question: Can I synthesise a component described in Verilog, obtain an EDIF, then write a VHDL wrapp...
2 comments posted 20yrs
posted by robin.bruce
2 comments posted 20yrs posted by robin.bruce

system design

hi,friends: I am a fresh man in IC design.How can I start my study in system design?I need ur suggestions.Can u commend...
1 comments posted 20yrs
posted by wuyi316904
1 comments posted 20yrs posted by wuyi316904

clock hold time problems reported in quartus II

Quartus II is reporting a clock hold time violation in a circuit which may be described by the following diagram: -----...
5 comments posted 20yrs
posted by oopere
5 comments posted 20yrs posted by oopere

tutorial searching

hi i am new whit this technology. so anyone have or know about a good tutorial of fpga vhdl etc... i bougth the spartan-...
3 comments posted 20yrs
posted by aresolimpico
3 comments posted 20yrs posted by aresolimpico

High-speed ADC+ Rocket I/O capability FPGA board

Hi everyone, I am looking to buy a board that has the following features: 1. High-speed ADC 2. Xilinx Virtex-2Pro or Vi...
4 comments posted 20yrs
posted by vivek.menon79
4 comments posted 20yrs posted by vivek.menon79

ISE 8.2i and EDK8.1i

Hi all, I would like to know before upgrade if EDK8.1i is compatible with ISE8.2i. Thanks in advance
6 comments posted 20yrs
posted by taileb.mehdi
6 comments posted 20yrs posted by taileb.mehdi

MIG DDR2 controller does not work (reset problems?)

Hi, I build a DDR2 controller using the Mig 1.5. In functional simulation everything works without problems (as alwayys...
11 comments posted 20yrs
posted by heinerlitz
11 comments posted 20yrs posted by heinerlitz