Hi, I build a DDR2 controller using the Mig 1.5.
In functional simulation everything works without problems (as alwayys). In the hardware implementation it does not work. I used the synthesizable testbench which is provided by the Mig. My design is driven by a 200Mhz Refclock and 125MHz system clock. I used chipscope and oscilloscope to figure out the following:
-All clocks (200, 90, 50) work properly. Also clk0 which controlls most part of the ddr2controller module.
-I can messure the correct RAM clock on the PCB
-After the reset WDF FIFO is empty and the internal writeWDF signal toggles untill the WDF almost full signal goes active. It stays high forever.
- The other signals on the PCB (or on chip using chipscope) especially (ras, cas, we, cs) do not toggle at all.
SO data is never written to the ram and never read out. The FIFO just runs full.
Did anybody experience similar problems and can help? The xilinx design only uses synchronous resets. These are regarded like normal signals by the router and hence do not meet the timing (high fan out probably). Is this ok? How are resets treated in FPGAs anyway? I always use asynchronous reset so they dont interfere with timing issues. Can i tell XST in anyway that it should treat reset signals properly? How to tell XST to make a reset tree synthesis? Could it be due to the FIFO16 bug? I dont think so, as it doesnt run at all. The controller should at least try to access the RAM several times, right?