Hi group, here's a question:
Can I synthesise a component described in Verilog, obtain an EDIF, then write a VHDL wrapper around it so as to integrate it into a greater VHDL project.
yours in ignorance,
Robin
Creating EDIF from Verilog, then using VHDL wrapper
Jul 20, 2006
2 Replies
Robin Bruce schrieb:
you should yes. most of the tools allow any mix of verilog-vhdl, but you can also use edif as interim format
antti
Robin
Coming from a similar direction is one of our TechiTips here
formatting link
It is a little bit old now but the module build up approach described is still applicable to mixed language application.
John Adair Enterpo> Hi group, here's a question:
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