Field-Programmable Gate Arrays

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Last Chance for Tarfessock1 Features

We have mentioned Tarfessock1 before and now at the last point where we can add features for the board. You know have t...
13 comments posted 20yrs
posted by removethisthenleavejea
13 comments posted 20yrs posted by removethisthenleavejea

[ANN] RHDL-0.5.0 released

RHDL 0.5.0 has been released! What is it? ============== RHDL (Ruby Hardware Description Language) is a DSL (Domain Spe...
1 comments posted 20yrs
posted by ptkwt
1 comments posted 20yrs posted by ptkwt

Inferring a Xilinx FIFO

I was just shown how to infer a Xilinx BRAM with a constant array. I used a counter to address it. Is there anyway to i...
2 comments posted 20yrs
posted by bradsmallridge
2 comments posted 20yrs posted by bradsmallridge

xess board problem (error downloading into ram)

Hi all, I downloaded code for a vga generator from xess design examples. I just want to verify that my board is functio...
2 comments posted 20yrs
posted by subhasri.krishnan
2 comments posted 20yrs posted by subhasri.krishnan

Sorting algorithm for FPGA availlable?

Hello, we have a Virtex4 FPGA and are looking for availlable hardware sorting algorithms. I couldnt find anything @open...
14 comments posted 20yrs
posted by heinerlitz
14 comments posted 20yrs posted by heinerlitz

VHDL Data Buffer on Spartan-3E

My application needs 4KB (32768 bits) of buffer space for incoming data. We are wanting to use the Spartan-3E, but we h...
1 comments posted 20yrs
posted by alexmchale
1 comments posted 20yrs posted by alexmchale

PCIe: use 8*x1 PHY devices to form x8

Hi all, We are about to implement a PCIe x8 core but don't want to make it on Virtex-4 FX devices, so the PHY layer sho...
2 comments posted 20yrs
posted by taileb.mehdi
2 comments posted 20yrs posted by taileb.mehdi

Synthesis Problems with Quartus II Version 6.x

Dear all, I recently jumped to Quartus 6.0 (from former 5.x) and experienced that the design would not compile correctl...
1 comments posted 20yrs
posted by fpgaengineerfrankfurt
1 comments posted 20yrs posted by fpgaengineerfrankfurt

Virtex 4 ACE Compact Flash configuration problem

I am trying to program Xilinx Virtex4 evaluation board ML402 via ACE using Compact Flash card. Every time when I turn th...
6 comments posted 20yrs
posted by dan_mr
6 comments posted 20yrs posted by dan_mr

ISE 8.2 - time to crash 20 minutes

Hi Xilinx software is getting better! With 8.1 release I managed to get first fatal crash within 5 minutes after instal...
3 comments posted 20yrs
posted by antti
3 comments posted 20yrs posted by antti

Which PCI core for Cyclone II board?

Does anyone have experience with more than one of the PCI cores out there? I'm working a PCI card that's still in the e...
19 comments posted 20yrs
posted by brian.mcf1985
19 comments posted 20yrs posted by brian.mcf1985