Latest threads in Field-Programmable Gate Arrays

ANN: Tyd-IP Code Generator adds NCO design capability

Hi, In adition to filter and fft creation, Tyd-IP Code Generator now generates VHDL for NCO design. Demo may be download...

0 20yrs

stenasc

0 20yrs stenasc

Last Chance for Tarfessock1 Features

We have mentioned Tarfessock1 before and now at the last point where we can add features for the board. You know have t...

13 20yrs

removethisthenleavejea

13 20yrs removethisthenleavejea

[ANN] RHDL-0.5.0 released

RHDL 0.5.0 has been released! What is it? ============== RHDL (Ruby Hardware Description Language) is a DSL (Domain Spe...

1 20yrs

ptkwt

1 20yrs ptkwt

Combining Schematic and VHDL code in Webpack 8.1 ??

Hello! I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL at the moment, and i have so far used V...

2 20yrs

per

2 20yrs per

Inferring a Xilinx FIFO

I was just shown how to infer a Xilinx BRAM with a constant array. I used a counter to address it. Is there anyway to i...

2 20yrs

bradsmallridge

2 20yrs bradsmallridge

xess board problem (error downloading into ram)

Hi all, I downloaded code for a vga generator from xess design examples. I just want to verify that my board is functio...

2 20yrs

subhasri.krishnan

2 20yrs subhasri.krishnan

Specify Clock Correction Sequence for Virtex-II ProX MGT (Rocket I/O X)

I have a problem while specifying the clock correction sequence for the Virtex-II ProX MGT. The problem is that I don't...

0 20yrs

no-replay

0 20yrs no-replay

Sorting algorithm for FPGA availlable?

Hello, we have a Virtex4 FPGA and are looking for availlable hardware sorting algorithms. I couldnt find anything @open...

14 20yrs

heinerlitz

14 20yrs heinerlitz

VHDL Data Buffer on Spartan-3E

My application needs 4KB (32768 bits) of buffer space for incoming data. We are wanting to use the Spartan-3E, but we h...

1 20yrs

alexmchale

1 20yrs alexmchale

PCIe: use 8*x1 PHY devices to form x8

Hi all, We are about to implement a PCIe x8 core but don't want to make it on Virtex-4 FX devices, so the PHY layer sho...

2 20yrs

taileb.mehdi

2 20yrs taileb.mehdi

Virtex-4 PowerPC and Trace32 ICD - start up help wanted

Hello, guys! Anyone has an experience debugging Virtex-4 PPC via Lauterbach TRACE32? I just can't connect them together...

0 20yrs

jackhab

0 20yrs jackhab

corrupted data when accessing dual port bram in Cyclone II

I am having several dual port block rams in a cyclone II device. The access takes place as simple dual port option with...

10 20yrs

fpgaengineerfrankfurt

10 20yrs fpgaengineerfrankfurt

Synthesis Problems with Quartus II Version 6.x

Dear all, I recently jumped to Quartus 6.0 (from former 5.x) and experienced that the design would not compile correctl...

1 20yrs

fpgaengineerfrankfurt

1 20yrs fpgaengineerfrankfurt

Virtex 4 ACE Compact Flash configuration problem

I am trying to program Xilinx Virtex4 evaluation board ML402 via ACE using Compact Flash card. Every time when I turn th...

6 20yrs

dan_mr

6 20yrs dan_mr

ISE 8.2 - time to crash 20 minutes

Hi Xilinx software is getting better! With 8.1 release I managed to get first fatal crash within 5 minutes after instal...

3 20yrs

antti

3 20yrs antti

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