IIR FPGA 'crosspost'

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I have posted on comp.dsp about this and got interesting answers. I
have just discovered this group so I would like to know if some of you
have something to add...

I have designed a 26 order IIR filter (13 biquads)

Someone proposed on comp.dsp to use direct form I saying that it's was
not the best structure for optimising the FPGA "space", the easiest to
design though.

I know that biquads implementation are better to control problems that
occurs with FPGA

By the way, I think that, when I will have succeed in designing a
efficient 2nd order cells on the FPGA, I will be able to do any order
of filters. As I will know how much "space" a single cell takes, I will

just need to connect these cells in cascade.

Do you think that Direct-Form (or even tranposed) I 2nd order
structures with a pipeline at 2*Freq is the best way to achieve such a

My sample rate is 18 Mhz.

Thanks for your help.

NB : The post on comp.dsp was titled "FPGA"

Re: IIR FPGA 'crosspost'
Modern FPGAs be clocked at 13x your 18 MHz sample rate.  Doing so lets
you share the same hardware for all 13 of your biquads, and also gives
you the benefit of allowing a 13 clock pipeline latency in the feedback
loops in the filter implementation.  If you use the embedded multipliers
that are common on many of the modern FPGAs, you should be able to
manage with 13 pipeline stages in the loop.  It may be a bit of a
challenge if it is a floating point implementation: in that case you can
use 2 instances, each handling 7 filters to get twice as much pipeline
latency around the loop, which should be ample for a floating point

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