Quartus II is reporting a clock hold time violation in a circuit which may be described by the following diagram:
-------- -------- d FF q--[logic]--d FF q -clk | -clk | | -------- | -------- | |
--o------------------
I understand that the problem is that the input d of the second FF changes too early after the common clock edge. However, somewhere else in the same circuit I have the following
-------- -------- d FF q-----------d FF q -clk | -clk | | -------- | -------- | |
--o------------------
and quartus II does _not_ report any hold time violation here, and obviously enough, the situation is even worse.
Something similar appears if I build a divide by 2: a) directly (inverted q to d) or b)using a 1 bit wide lpm_counter. In the first case, I get a hold time violation and everything is ok in the second case.
Perhaps someone can provide some insight into the following questions:
- Is something inherently wrong with the first schematic? I even thought it was always good idea to resynchronize signals in a similar way.
- In case this approach is ok, why does quartus II report clock hold time problems?
- If applicable, what should I tell the quartus II timing analyzer to get rid of this error?
Thanks, Pere