Field-Programmable Gate Arrays

Minimum frequency at which ddr can operate

Hi, I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. And i am using the controller generated by the MIG1....

4 comments posted 20yrs

posted by subin.82

4 comments posted 20yrs posted by subin.82

How do I pass on an integer to a task and compare with an integer in the task?

I used [31:0] to pass on the integer to my task, but it won't compare with "count" which is of integer type. How can I...

6 comments posted 20yrs

posted by Mr. Ken

6 comments posted 20yrs posted by Mr. Ken

Generate statements for I/O list

Greetings, I want to parameterize a module in a way that makes some inputs used or not used. If I have the input define...

2 comments posted 20yrs

posted by johnhandwork

2 comments posted 20yrs posted by johnhandwork

Programmable pulse generator

Hi All, I'm trying to develop a programmable pulse generator, essentially a single pulse of variable width repeated at...

13 comments posted 20yrs

posted by jimwalsh142

13 comments posted 20yrs posted by jimwalsh142

Implementing Haar Decomposition on 256 sample input using only sysgen blocks

Hi everyone, i m trying to implement the haar basis decomposition ona big signal and need to build a model using Xilinx...

1 comments posted 20yrs

posted by sirisha.aluru

1 comments posted 20yrs posted by sirisha.aluru

FPGA LABVIEW programming

Hello, National instruments has introduced new module in their labview 8 for programming the xilinx FPGA chips. It conv...

9 comments posted 20yrs

posted by conphiloso

9 comments posted 20yrs posted by conphiloso

XPS 7.1 to 8.1 Warnings

Hi, I am working with a project from Memec for the Virtex-4 FX12. The directory name has a 7.1 after the name of the pr...

3 comments posted 20yrs

posted by kyle.hable

3 comments posted 20yrs posted by kyle.hable

Where are Huffman encoding applications?

Hi, I want to know how many fields Huffman encoding thoery are used. As I can counted, 1. In Window operating system, s...

16 comments posted 20yrs

posted by wtxwtx

16 comments posted 20yrs posted by wtxwtx

Virtex4 ML455 do you know this board?... help me!

Thanks anticipate ... i have bought ML455 board... but that haven't documentation... someone can help me???? Bye.

0 comments posted 20yrs

posted by donatopace

0 comments posted 20yrs posted by donatopace

FPGA : BUG in ISE- View RTL Schematics ?

Hi I am viewing the RTL schematic generated by the Xilinx ISE (7.1 with SP$)tool for a vhdl statement

2 comments posted 20yrs

posted by pbijoy

2 comments posted 20yrs posted by pbijoy

Usage of DDR IOBs

Hello all, I intend the demultiplex the data coming to the FPGA on dual-edge clock using the DDR Input Buffers. However...

4 comments posted 20yrs

posted by venkat.japan

4 comments posted 20yrs posted by venkat.japan

Quick way to change Xilinx BRAM init values

I infer a Xilinx BRAM with a VHDL constant array. But when I change a single value in this array, ISE resynthesizes the...

4 comments posted 20yrs

posted by bradsmallridge

4 comments posted 20yrs posted by bradsmallridge

Lattice Blogs

Lattice has launched a new blog called "Frontier" at http://www.latticeblogs.typepad.com/ Frontier is a collaborative b...

4 comments posted 20yrs

posted by bart.borosky

4 comments posted 20yrs posted by bart.borosky

S3E USB2.0 port

Hi all, Did anyone use USB2.0 port of Spartan3E Starter Kit for his own purpose? If course this includes unsoldering of...

7 comments posted 20yrs

posted by ales.gorkic

7 comments posted 20yrs posted by ales.gorkic

DDR2 SRAM Stratix II questions

I posted this last week, but it has yet to show up on google groups, so I fear my news server isn't as healthy as I wou...

12 comments posted 20yrs

posted by eric.amundsen

12 comments posted 20yrs posted by eric.amundsen