Latest threads in Field-Programmable Gate Arrays

Xilinx: Initializing BRAM content in the ngc

Hello, I'd like to know if it's possible (and if yes how ?) to initialize BRAM content not directly in the sources, nor...

1 20yrs

SomeOne

1 20yrs SomeOne

Minimum frequency at which ddr can operate

Hi, I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. And i am using the controller generated by the MIG1....

4 20yrs

subin.82

4 20yrs subin.82

How do I pass on an integer to a task and compare with an integer in the task?

I used [31:0] to pass on the integer to my task, but it won't compare with "count" which is of integer type. How can I...

6 20yrs

Mr. Ken

6 20yrs Mr. Ken

Generate statements for I/O list

Greetings, I want to parameterize a module in a way that makes some inputs used or not used. If I have the input define...

2 20yrs

johnhandwork

2 20yrs johnhandwork

Programmable pulse generator

Hi All, I'm trying to develop a programmable pulse generator, essentially a single pulse of variable width repeated at...

13 20yrs

jimwalsh142

13 20yrs jimwalsh142

Implementing Haar Decomposition on 256 sample input using only sysgen blocks

Hi everyone, i m trying to implement the haar basis decomposition ona big signal and need to build a model using Xilinx...

1 20yrs

sirisha.aluru

1 20yrs sirisha.aluru

FPGA LABVIEW programming

Hello, National instruments has introduced new module in their labview 8 for programming the xilinx FPGA chips. It conv...

9 20yrs

conphiloso

9 20yrs conphiloso

XPS 7.1 to 8.1 Warnings

Hi, I am working with a project from Memec for the Virtex-4 FX12. The directory name has a 7.1 after the name of the pr...

3 20yrs

kyle.hable

3 20yrs kyle.hable

Where are Huffman encoding applications?

Hi, I want to know how many fields Huffman encoding thoery are used. As I can counted, 1. In Window operating system, s...

16 20yrs

wtxwtx

16 20yrs wtxwtx

Virtex4 ML455 do you know this board?... help me!

Thanks anticipate ... i have bought ML455 board... but that haven't documentation... someone can help me???? Bye.

0 20yrs

donatopace

0 20yrs donatopace

FPGA : BUG in ISE- View RTL Schematics ?

Hi I am viewing the RTL schematic generated by the Xilinx ISE (7.1 with SP$)tool for a vhdl statement

2 20yrs

pbijoy

2 20yrs pbijoy

Usage of DDR IOBs

Hello all, I intend the demultiplex the data coming to the FPGA on dual-edge clock using the DDR Input Buffers. However...

4 20yrs

venkat.japan

4 20yrs venkat.japan

Quick way to change Xilinx BRAM init values

I infer a Xilinx BRAM with a VHDL constant array. But when I change a single value in this array, ISE resynthesizes the...

4 20yrs

bradsmallridge

4 20yrs bradsmallridge

Lattice Blogs

Lattice has launched a new blog called "Frontier" at http://www.latticeblogs.typepad.com/ Frontier is a collaborative b...

4 20yrs

bart.borosky

4 20yrs bart.borosky

S3E USB2.0 port

Hi all, Did anyone use USB2.0 port of Spartan3E Starter Kit for his own purpose? If course this includes unsoldering of...

7 20yrs

ales.gorkic

7 20yrs ales.gorkic

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