FPGA : BUG in ISE- View RTL Schematics ?

Hi I am viewing the RTL schematic generated by the Xilinx ISE (7.1 with SP$)tool for a vhdl statement

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Hi, AND2, AND2B1, AND2B2 are 3 types of AND2.. When XST infers any one of these 3, schematic editor gives it name as simple AND2.. AND2 : O

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Hi Bijoy, no, it's a beetle. Because it's so old. :-)

In 7.1 the rtl schematics became oversimplified, and had no inverted inputs anymore. I hope the newer versions behave better, but i haven't tested it.

have a nice synthesis Eilert

bijoy schrieb:

SP$)tool for a vhdl statement

to the AND gate as 'A' , 'B'.

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