Greetings,
I want to parameterize a module in a way that makes some inputs used or not used. If I have the input defined but don't use it in the module instantiation, I end up with a synthesis warning about tying an unused input to 0. If I use a generate, I'll be trying to add a generate item of the form "input clk," where the comma looks like it won't be a legal generate item.
Anyone have a clean way to remove the input from the module definition list without a `define?
I can imagine specifying a Verilog-1995 style I/O list where only the names are listed initially then outside the module port definition use an if/else to define my value as input or output; if I don't use the output, I get no warning and if I hook something up to the signal I want unused I should have a synthesis warning for too many drivers. But I'd like to keep my Verilog-2001 style of I/O definitions embedded in the portdefs.
- John_H