Field-Programmable Gate Arrays

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DDR2 SRAM Stratix II questions

I posted this last week, but it has yet to show up on google groups, so I fear my news server isn't as healthy as I wou...
12 comments posted 20yrs
posted by eric.amundsen
12 comments posted 20yrs posted by eric.amundsen

MIG 1.6 DDR2 testing problems (FIFO16 related?)

Hi, I finally got to run the MIG created DDR2 for VIrtex4 devices controller. However I have two problems with the cont...
13 comments posted 20yrs
posted by heinerlitz
13 comments posted 20yrs posted by heinerlitz

Ethernet wrapper IP core with ML403

Hello, I would like to try the Ethernet Wrapper IP core together with the ml403 board and I have a problem making it op...
0 comments posted 20yrs
posted by misiu75
0 comments posted 20yrs posted by misiu75

100m JTAG cable

This might be slightly OT for an FPGA group, but maybe someone has run into a similar problem before: I'd like to conne...
26 comments posted 20yrs
posted by johannes.vanderhorst
26 comments posted 20yrs posted by johannes.vanderhorst

Low Cost FPGA Charge Pump Power supply

New TechiTip added to our website for a 5p (GBP) or 10c (US) FPGA based charge pump power supply. You will find it here...
2 comments posted 20yrs
posted by removethisthenleavejea
2 comments posted 20yrs posted by removethisthenleavejea

Core Generator

I have recieved some Verilog code with a Xilinx coregen module calle BLKMEMDP_V6_1 and ASYNC_FIFO_V5_1. I presume these...
1 comments posted 20yrs
posted by maxascent
1 comments posted 20yrs posted by maxascent

Problems compiling with ISE Webpack 8.2.01i

Hello Freinds. I am a newcomer to the field of programmable logic devices and I am currently trying to teach myself VHD...
8 comments posted 20yrs
posted by aijazbaig1
8 comments posted 20yrs posted by aijazbaig1

Problem with assigning package pins using PACE

Hi, When I use PACE to assign package pins in ISE 7.1, instead of all my pins being displayed as usual, the only pins d...
0 comments posted 20yrs
posted by alastairlynch
0 comments posted 20yrs posted by alastairlynch

Accessing one SDRAM from two MicroBlazes

Hello experts and newsgroup, I'm planning a new embedded design. The first MicroBlaze handles the communication to exte...
8 comments posted 20yrs
posted by Ben.Marpe
8 comments posted 20yrs posted by Ben.Marpe

Interfacing Spartan3 FPGA to 5V PCI

Hi, is setting the Vcco of Spartan3 banks to +3.3V would allow the FPGA to work with a 5V signaling environment like 5V...
3 comments posted 20yrs
posted by yy7d6
3 comments posted 20yrs posted by yy7d6

large data access to SDRAM at fixed frequency

Hi ! I am new in electronique. I want to make an analog acquisition board with an ARM microcontroler ( Samsung S3C44B0x...
3 comments posted 20yrs
posted by pm.boyer
3 comments posted 20yrs posted by pm.boyer