Quick way to change Xilinx BRAM init values

I infer a Xilinx BRAM with a VHDL constant array. But when I change a single value in this array, ISE resynthesizes the entire design. There must be a quicker way.

Brad Smallridge aivision

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Brad Smallridge
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Depending on your target device, you can easily reverse-engeneer the bitstream and update the BRAM values in there directly. I think xilinx themselves provide info about how to do this. I'm sure they do for LUT table values. This may be more worry than you want, though.


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Hi Brad, look for Informations about the DATA2MEM tool. Then you can change your Memory contents and generate new Bitfiles in an instant.

The documentation is a little poor, but hter's lot's of stuff in this group about it.

Have a anice synthesis Eilert

Brad Smallridge schrieb:

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Hi Brad, That DATA2MEM tool sound like the way to go, must check it out.

I suspect (haven't tried it) you could use the FPGAEditor with a command such as:

setattr comp onchip_ram_top/block_ram_1/BU5 INIT_01


This would avoid synthesis and par, somewhat similar to the DATA2MEM tool.

It is also probably also worth mentioning that you can put an entry in your UCF file such as:

INST "onchip_ram_top/block_ram_1/BU5" INIT_01=


This way you still have to PAR after changes but don't need to resynthesize. I would imagine this would override initialization values set in the hdl.



backhus wrote:

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Vivian Bessler


Yet another equivalent possibility would be to do the same on the XDL file and to convert back to the ncd.


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