Hi, I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga. And i am using the controller generated by the MIG1.5 tool. When i run this controller in the real hardware i am getting zeros in the result bus(read_data_fifo_out)... Dont know where i am wrong. I am monitored all my controller signals using the chipscope and they are all working fine for me. But the ddr is not giving anything back... Can u guys please tell me what is the minimum frequency at which i can operate the ddr controller. regards subin
- posted
16 years ago