Hello all, I intend the demultiplex the data coming to the FPGA on dual-edge clock using the DDR Input Buffers. However I could not find an appropriate explanation of instantiating the DDR Input buffer for this purpose. I am using the DCM to generate the CLK0 and CLK180 using the data reference clock that comes with the data at the Input boundary. Any of your comments/suggestions are sincerely appreicated.
you just instantiate the iddr buffer and drive it with a single SDR clock. You dont need the 180phase clk. The idddr then provides the data on the two output data busses. One data value at the positive clk edge and one at the negative clock edge.
Hello Heiner, Thanks for your response. I guess this option of IDDR will work for Virtex 4 FPGA. However my FPGA of interest is Virtex II Pro. I am sorry for not mentioning the type of device in my earlier mail. I will appreciate your further suggestions.
I believe you can infer input DDR flops, at least in Verilog. You need to be careful since the Xilinx tools are picky about infering IOB registers - if you don't do thing just right, the tools won't infer the registers in the IOB.
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