Linear priority encoder in Xilinx Virtex4

Sylvain Munaut schrieb:

was possible meant as brain teaser!

Antti

Let me try to verbally sketch this out for you for 4 bits: Imagine two colums of luts. There is one lut on the left for 4 inputs and 4 on the right one for each output. The left LUT is a 4 input OR and all the LUTs on the right are AND gates but with bubbles on some inputs. The top right LUT is just an AND of top first input bit and the output of left LUT. The second LUT on the right has first input inverted, second bit and output of left LUT. The third LUT has first two inputs inverted, third input, and output of left LUT. The last LUT has the first 3 inputs inverted and output of left LUT. This gives you

Thanks ! Exactly what I was looking for ;)

Sylvain

Well, actually I'm having trouble with the chaining ... how do you implement what you describe (masking the lower priority OR luts) when a higher one is active.

I have the slice schema before me and I can't figure that out ... (damn, am I slow today ...)

I see that : - I could chain two stages, but no more than two. - I could use a big or of all the upper priority groups with the carry chain and then use it to mask the left OR. But then for 3 groups, I would need : - Upper priority group : - Just 1 LUT4 for the OR + 4 LUT4 for encoding - Middle priority group : - 1 LUT4 for the OR + 1 LUT4 for the 'masking' + 4 LUT4 for encoding - Low priority group - 1 LUT4 for the OR + 2 LUT4 for the masking +

So that would be 18 LUT4.

And 5*3 + 1 = 16; So there is better ;)

Sylvain