Field-Programmable Gate Arrays

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Block RAM vs Flip Flop

In the following (use a font with fixed width to display it rightly) +-------------/--------+ | 32 | | ___ | +----| \ |...
4 comments posted 19yrs
posted by sdroamt
4 comments posted 19yrs posted by sdroamt

Checking syntax

Hi all! Is there a way to check the syntax of an HDL file using Xilinx command line tools? Thanks in advance
1 comments posted 19yrs
posted by taileb.mehdi
1 comments posted 19yrs posted by taileb.mehdi

Global signal conservation

Hi, In opencores DDR implementation, the author uses a PLL to generate a clock of multiple phases. The PLL outputs true...
6 comments posted 19yrs
posted by dash
6 comments posted 19yrs posted by dash

esoteric hardware?

Hello. By the way, does anybody here have enough sense of humor to build esoteric hardware using FPGA? Esoteric hardwar...
4 comments posted 19yrs
posted by hypermodest
4 comments posted 19yrs posted by hypermodest

USB PHYs and drivers that folks have used

I'm putting together a system that requires a USB host and a USB device interface (two separate interfaces). On the 'de...
4 comments posted 19yrs
posted by Kevin.Jennings
4 comments posted 19yrs posted by Kevin.Jennings

Xilinx Virtex-4FC PPC

Hi. Did anybody have a problem of "loosing" PPC during debugging? My software crashes but when I click Stop on GDB or P...
0 comments posted 19yrs
posted by shteinman
0 comments posted 19yrs posted by shteinman

fastest FPGA

Hello. I've a task to make attempt to crack some cryptographical hash-function by using brute-force attack. So I wish t...
108 comments posted 19yrs
posted by hypermodest
108 comments posted 19yrs posted by hypermodest

DQPs

HI, could you tell me what is DQPx in CY7C1386C (SRAM)? There are 36 bits of datas.. 32 DQx and 4 DOPx.. Thanks zlotawy
3 comments posted 19yrs
posted by spawnek
3 comments posted 19yrs posted by spawnek

Timing

Hi I have a design that I have verified using a post route simulation an then PAR the design with no timing errors. Do...
4 comments posted 19yrs
posted by maxascent
4 comments posted 19yrs posted by maxascent

Xilinx Floorplanner

What is the best source for learning about the Xilinx floorplanner? I see stuff in the constraints documentation but th...
3 comments posted 19yrs
posted by bradsmallridge
3 comments posted 19yrs posted by bradsmallridge

virtex4fx board and ethernet

Hi all, i'm wondering if someone knows if it does exist a cheap virtex4fx based card with at least 2 10/100/1000 etherne...
7 comments posted 19yrs
posted by sdroamt
7 comments posted 19yrs posted by sdroamt

Modelsim

Hi Does has anyone experienced problems with modelsim running slowly? I a not talking about simulation speed but rather...
3 comments posted 19yrs
posted by maxascent
3 comments posted 19yrs posted by maxascent

Microblaze : xil_malloc malloc

Hi I want to allocate memory but it doesn't work. If I use xil_malloc I can not allocated enough memory, pointer to NUL...
1 comments posted 19yrs
posted by
1 comments posted 19yrs posted by