I'm having problems instantiating my EDK file within an ISE project.
I have a top level VHDL that looks like:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all;
entity topnew is end topnew;
architecture RTL of topnew is
begin
COMPONENT system PORT( fpga_0_RS232_Uart_RX_pin : IN std_logic; fpga_0_DDR_CLK_FB : IN std_logic; sys_clk_pin : IN std_logic; sys_rst_pin : IN std_logic; PortName : IN std_logic; fpga_0_LEDs_4Bit_GPIO_IO_pin : INOUT std_logic_vector(0 to 3); fpga_0_LEDs_Positions_GPIO_IO_pin : INOUT std_logic_vector(0 to 4); fpga_0_Push_Buttons_Position_GPIO_IO_pin : INOUT std_logic_vector(0 to 4); fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin : INOUT std_logic_vector(0 to 3); fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin : INOUT std_logic_vector(0 to 31); fpga_0_SRAM_256Kx32_Mem_DQ_pin : INOUT std_logic_vector(0 to 31);
fpga_0_RS232_Uart_TX_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin : OUT std_logic_vector(0 to 12); fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin : OUT std_logic_vector(0 to
1); fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin : OUT std_logic; fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin : OUT std_logic_vector(0 to 3); fpga_0_SRAM_256Kx32_Mem_A_pin : OUT std_logic_vector(9 to 29); fpga_0_SRAM_256Kx32_Mem_BEN_pin : OUT std_logic_vector(0 to 3); fpga_0_SRAM_256Kx32_Mem_WEN_pin : OUT std_logic; fpga_0_SRAM_256Kx32_Mem_OEN_pin : OUT std_logic_vector(0 to 0); fpga_0_SRAM_256Kx32_Mem_CEN_pin : OUT std_logic_vector(0 to 0); fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin : OUT std_logic; fpga_0_SRAM_CLOCK : OUT std_logic ); END COMPONENT;Inst_system: system PORT MAP( fpga_0_RS232_Uart_RX_pin => , fpga_0_RS232_Uart_TX_pin => , fpga_0_LEDs_4Bit_GPIO_IO_pin => , fpga_0_LEDs_Positions_GPIO_IO_pin => , fpga_0_Push_Buttons_Position_GPIO_IO_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin => , fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin => , fpga_0_SRAM_256Kx32_Mem_A_pin => , fpga_0_SRAM_256Kx32_Mem_BEN_pin => , fpga_0_SRAM_256Kx32_Mem_WEN_pin => , fpga_0_SRAM_256Kx32_Mem_DQ_pin => , fpga_0_SRAM_256Kx32_Mem_OEN_pin => , fpga_0_SRAM_256Kx32_Mem_CEN_pin => , fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin => , fpga_0_SRAM_CLOCK => , fpga_0_DDR_CLK_FB => , sys_clk_pin => , sys_rst_pin => , PortName =>
);
end architecture RTL;
-----------
But I get these errors:
Compiling vhdl file "D:/comp8_xmp_ise/comp8/topnew.vhd" in Library work. ERROR:HDLParsers:164 - "D:/comp8_xmp_ise/comp8/topnew.vhd" Line 37. parse error, unexpected COMPONENT ERROR:HDLParsers:164 - "D:/comp8_xmp_ise/comp8/topnew.vhd" Line 40. parse error, unexpected IN ERROR:HDLParsers:164 - "D:/comp8_xmp_ise/comp8/topnew.vhd" Line 41. parse error, unexpected IN