Field-Programmable Gate Arrays

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FPGA timing

Hi, I am porting my design from ASIC to FPGA, but I found the timing in FPGA is very bad. What I konw is to set up the...
9 comments posted 19yrs
posted by chenyong20000
9 comments posted 19yrs posted by chenyong20000

xilinx bram instantation template in vhdl?

I want to create a 1152 by 6 bit rom and I want to use a bram. It can be clocked or not clocked, but I'd prefer not clo...
11 comments posted 19yrs
posted by dash
11 comments posted 19yrs posted by dash

Simulating EDK 8.1i System using ModelSim 6.1e

Hello, Recently, I have been trying to simulate my system to verify that the pieces are working correctly in my EDK pro...
6 comments posted 19yrs
posted by kits59
6 comments posted 19yrs posted by kits59

VHDL or Verilog or SystemC?

hello all, I have experience with ARM microcontroller in C/C++ programming, now job function force me to have to expand...
5 comments posted 19yrs
posted by jetq5188
5 comments posted 19yrs posted by jetq5188

Lattice eval board with PCIe and SATA

Hi http://www.latticesemi.com/products/developmenthardware/fpgafspcboards/scpciexpressx1evaluationb.cfm I wonder if tha...
2 comments posted 19yrs
posted by Antti.Lukats
2 comments posted 19yrs posted by Antti.Lukats

Problem with adding DCM to Spartan-3

Hi, I have a fairly simple Spartan-3 design which essentially implements an interface to an external MCU and it works f...
1 comments posted 19yrs
posted by dave.bryan
1 comments posted 19yrs posted by dave.bryan

RESET Signals

Why RESET signals are always active low? I understand that active low resets are immune to noise, but could someone expl...
6 comments posted 19yrs
posted by hpsham
6 comments posted 19yrs posted by hpsham

Functional and Post-Synthesis Simulation

Which is the difference between Functional and Post-Synthesis Simulation? Why should I do both simulation? Thanks Peppe
3 comments posted 19yrs
posted by peppe
3 comments posted 19yrs posted by peppe

Trying to get plb_temac working

Hello, I am using the XilinX Virtex 4 FX 12 Evaluation Kit and want to get ethernet working (it will have to do some IP...
13 comments posted 19yrs
posted by benedikt
13 comments posted 19yrs posted by benedikt

Can someone erase my EPM7064s ?

I have 20 Altera EPM7064SLC44s that apparently have had their JTAG pins disabled, and can therefore only be erased by a...
0 comments posted 19yrs
posted by kortink
0 comments posted 19yrs posted by kortink

X4000 bad configuration

HI, I experience configuration problems with XC4010E parts. I configure them in slave serial mode : M0,M1,M2 = Z. Confi...
20 comments posted 19yrs
posted by rxnd
20 comments posted 19yrs posted by rxnd

Trace under High-Speed Signal

Hi, Are there anyone here that is familiar with signal integrity concepts? I'm running a trace (TDI for configuration)...
1 comments posted 19yrs
posted by yy7d6
1 comments posted 19yrs posted by yy7d6

HOLD violations in Xilinx fpga

Are there any approaches or constraints available to fix hold-time violations in the Xilinx ISE tool aimed at Virtex-2...
5 comments posted 19yrs
posted by szohair
5 comments posted 19yrs posted by szohair