I want to create a 1152 by 6 bit rom and I want to use a bram. It can be clocked or not clocked, but I'd prefer not clocked. Can someone point me to a template?
Something like this takes a long time to synthesize... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;
entity fontrom is port ( addr : in unsigned ( 10 downto 0); data : out std_logic_vector ( 5 downto 0) ); end fontrom;
architecture rtl of fontrom is begin
process ( addr) begin case addr is when "00000000000" => data data data data data data data data data data data data
Tues Nov 13 2001 Mike Treseler suggests something, see my attempt below. This synthesizes quickly but doesn't seem to use a BRAM, it uses 400+ LUTs to do it...want to use BRAMS as they're unused, and LUT's are in short supply...
-Dave
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;
entity fontrom is port ( addr : in unsigned ( 10 downto 0); data : out std_logic_vector ( 5 downto 0) ); end fontrom;
architecture rtl of fontrom is type small_rom is array (0 to 1151) of std_logic_vector(5 downto 0); constant this_rom : small_rom := ( 0 => "000000", 1 => "000000", 2 => "000000", 3 => "000000", 4 => "000000", ... 1143 => "111111", 1144 => "111111", 1145 => "111111", 1146 => "111111", 1147 => "111111", 1148 => "111111", 1149 => "111111", 1150 => "111111", 1151 => "111111", others => "000000" ); begin data
If you can infer the brams from a constant as shown earlier, it will simulate much faster than instantiated BRAMS. Also, the code would be portable to other architectures/vendors.
I just finished an 8 by 8 bit font for hex nibble outputs, 0 to F. I did this for a Xilinx Virtex4 SX35 ML402 dev board in VHDL. The code below might give you some ideas about how to proceed. You can see the font better if you replace the 0s with periods, and back again, when you are ready to synthesize.
Brad Smallridge Ai Vision
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VComponents.all;
entity vga_font is port ( clk : in std_logic; rst : in std_logic; addr : in std_logic_vector(14 downto 0); q : out std_logic ); end vga_font;
architecture behavioral of vga_font is
type init_array_type is array(natural range ) of bit_vector(7 downto 0); constant vga_font_data : init_array_type :=(
function stuff_it ( init_array : init_array_type; init_xx : integer ) return bit_vector is variable result : bit_vector(255 downto 0); variable i : integer ; variable j : integer ; variable temp : bit_vector(7 downto 0); begin result := X"0000000000000000000000000000000000000000000000000000000000000000"; i := 0 ; j := 32*init_xx ; while( (j < init_array'length) and (i 0, -- Optional output registers on the A port (0 or 1) DOB_REG => 1, -- Optional output registers on the B port (0 or 1) INIT_A => X"000000000", -- Initial values on A output port INIT_B => X"000000000", -- Initial values on B output port INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE) INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE) RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 READ_WIDTH_B => 1, -- Valid values are 1,2,4,9,18 or 36 SIM_COLLISION_CHECK => "ALL", -- "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
port map ( CASCADEOUTA => open, -- 1-bit cascade output CASCADEOUTB => open, -- 1-bit cascade output DOA => open, -- 32-bit A port Data Output DOB => dob, -- 32-bit B port Data Output DOPA => open, -- 4-bit A port Parity Output DOPB => open, -- 4-bit B port Parity Output ADDRA => (others=>'1'), -- 15-bit A port Address Input ADDRB => addr, -- 15-bit B port Address Input CASCADEINA => '0', -- 1-bit cascade A input CASCADEINB => '0', -- 1-bit cascade B input CLKA => '0', -- Port A Clock CLKB => clk, -- Port B Clock DIA => (others=>'1'), -- 32-bit A port Data Input DIB => (others=>'1'), -- 32-bit B port Data Input DIPA => (others=>'1'), -- 4-bit A port parity Input DIPB => (others=>'1'), -- 4-bit B port parity Input ENA => '0', -- 1-bit A port Enable Input ENB => '1', -- 1-bit B port Enable Input REGCEA => '0', -- 1-bit A port register enable input REGCEB => '1', -- 1-bit B port register enable input SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input WEA => (others=>'0'), -- 4-bit A port Write Enable Input WEB => (others=>'0') ); -- 4-bit B port Write Enable Input
q I want to create a 1152 by 6 bit rom and I want to use
Thanks. It looks too specific to xilinx though. When I added a clock the brams got inferred automatically. See sample below. The address input would have to be character# * font_row, and the result is a 6 bit strip for that row.
0 "000000", 4 => "000000", 5 => "000000",
-- font data deleted for brevity, font is 6x12, ascii characters from
0x20 to 0x7f 1145 => "111111", 1146 => "111111", 1147 => "111111", 1148 => "111111", 1149 => "111111", 1150 => "111111", 1151 => "111111", others => "000000" ); begin process(clk) begin if clk'event and clk = '1' then data
I was not aware of this document. It looks very useful, but it seems to be a bit out of date. It does not mention a number of newer families including Spartan 3. I guess the information applies as appropriate depending on the feature.
Will Xilinx be updating this document anytime soon?
Yes, many of the sources for different versions are found on the Xilinx web site. A google search turned up several and I figured out this link which is likely to be the latest, with a (likely incorrect) copyright date of 2005.
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