RESET Signals

Why RESET signals are always active low? I understand that active low resets are immune to noise, but could someone explain in detail?

Also

How does Power on Rest Work?

Thanks

Roger schrieb:

Reset signals are not _always_ low. But it allows an easy power on reset, as you need only a RC network to delay VCC for a few us-ms. As long as VCC is low, you have no problem, as no chip works without VCC. If VCC rises, you only need to delay the rising on reset until your chip is full powered and clock starts working.

bye Thomas

Resets are _often_ low for the reason already stated - it makes forcing a reset at power up very simple. That said, I have in a current design

2 devices that require active high resets.

Power-on reset (as found in many microcontrollers) can be achieved quite simply with a very basic (two transistor) flip-flop where the power up state is guaranteed by the simple artifice of delaying a signal or a small amount of capacitance on one side of the device. This usually does not require an external reset signal but the technique is the same; hold one particular line [low | high] during power-up, where power-up is defined as rising through some threshold. Brownout-detect uses the same principle.

For FPGAs, the power-on state is guaranteed by the init state of the loaded bitstream. Here we simply force an initialisation if the system voltage[s] drop below some threshold, but the effect is the same.

Cheers

PeteS

Cheers

PeteS

In the days of 5v ttl signals on boards, active low signals had more noise immunity than active high signals (assuming it is worse for noise to make a false signal true, than the other way around). Now, with

3.3V signals, there is a very small difference in the noise margings between levels, and with 2.5V logic and below, there is none.

If you consider 5V TTL logic, most drivers can be pulled up to to nearly 5V with a resistor, giving nearly 3 volts of headroom before falling below the minimum high-level threshold at the receiver. With a low driven signal, at 0.4V, it is hard to put a big enough resistor (small enough value) on the signal to pull it below 0.2 volts or so (otherwise the driver would not be able to drive the signal high against such a resistor). So it would only take a noise spike of 0.6 V to get above the maximum low threshold at the receiver, where, under just the wrong circumstances (remember Murphy!), it could be considered a high level input.

Andy

Roger wrote:

I should add that relying on RC networks driving digital inputs for power up resets is not a reliable practice, especially with fast, low voltage logic. The slow rise time causes high power dissipation, noise, and multiple transitions in and out of reset, leading to eratic operation.

I have also seen cases where a 2.5V processor actually executed random code when VCC > 1.0 V, which was lower than the reset circuit could guarantee a valid output. Purpose-made power up reset circuits that guarantee reset outputs down to VCC >= 0.8V are necessary in such cases.

Andy

Andy wrote:

Many signals in the discrete-logic days were active low, and still are, out of habit. Most decoder chips, for example, have active-low outputs. SRAM chips therefore have active-low enable inputs, to work with them. The reason actually predates TTL. Before TTL was DTL (diode-transistor logic), in which a wired-AND was the norm: that is, 2 or more transistors to ground, & a common pullup resistor. So the Low output impedance (a saturated transistor) is much lower than the High output (the resistor). Better noise tolerance.