VHDL or Verilog or SystemC?

If your job is forcing you to expand, I'd say you should use the language that's prevalent in your company. AFAIK the choice between Verilog and VHDL is somewhat arbitrary -- most people I know who favor one over the other choose which ever one they learned first. VHDL seems to be more amenable to structured design -- but I can't say because I only know Verilog.

What I _can_ say is that if you fall into a group of ten FPGA folks who all use language A and you only know language B, you should learn language A quick, because you're not going to be productive using the 'wrong' thing.

As for System C or Handel C -- I'm a luddite, so I view them with deep suspicion. I read magazine articles about them being used successfully, but I have yet to see widespread adoption, particularly in the FPGA world.

I'm in the same boat, however my reasons for wanting to get into FPGA use are more personal as opposed to required by the company.

I chose VHDL almost automatically. Verilog I recall suffered from complications when the project gets very big -- it isn't as strong as VHDL in putting separate components together to form a whole. Note I'm completely unfamiliar with Verilog, and the complaint above came from some other source.

I've heard lots of complaints about VHDL and I've got a few of my own. I'm just barely getting the hang of it, I can read it better than I can write it. I'm still trying to work out a style of my own. However it just seems to me time spent getting to know VHDL won't be wasted.

Important thing -- don't give up! It may seem very frustrating at first but remember everything will get worked out in the end. My big fear was something like "Oh god, this is just so ugly. I can't see myself having to do ugly things all the time...forget it." In the end it's not really ugly...just unfamiliar.

-Dave

Generally Europe uses VHDL and the US uses Verilog. I would suggest you use the one which is most likely to be used by your potential future employers.

There's enough of both (at least in the US) that unless you're trying for a specific employer it would be a good idea to learn one thoroughly, and learn at least a little bit of the other.

In addition to all the good advice you have received so far I would add to not ignore SystemC. It is indeed correct that if your company is doing low complexity FPGA work than SystemC might be a slight overkill :-). However, if your company is doing complex SoC stuff than SystemC (and SystemVerilog) knowledge might be a very useful asset. Not sure were you are based but at least in the UK verification engineers get generally better paid that FPGA RTL designers.

Hans