Functional and Post-Synthesis Simulation

The basic difference between functional and post-synthesis simulation is that functional simulation only check the behaviour of your design. It does not point out any race conditions that might occur in your design. Post-synthesis simulation is the simulation of your design after it has been synthesized, which means, that your design has been converted to gates and takes timing(propagation delays, setup and hold delays) into account. This simulation sheds light into race conditions or any other timing issues that might exist in your design which werent apparent in the behaviour simulation. Personally, I perform behavioural(functiona) simulation to check if the design is working properly and then perform timing(post-synthesis) simulation to check for timing violations, race conditions, etc. Hope this helps

It might shed light but it most likely will not since there is no expectation that the simulation will hit any of the corner conditions. Furthermore, timing simulations do not take into account any sort of variability of timing (i.e. min delay here, max delay there it simply uses all min, or all max or all typ). While you can argue that on a single chip you probably won't have a mix of mins and max you can't argue that there will be no variation (i.e. say 80% - 130% of typical). To check for correct timing you perform static timing analysis which does not require any simulation.

I'd suggest you perform static timing analysis instead...it is typically an output report of the synthesis operation.

KJ

Timing simulation by itself does not guarantee that you will catch all timing problems. You only catch the timing problems that match the timing of the test your are running. In addition, the delays in the model are generally the maximum delay, not the worst case (meaning minimum or maximum depending on the circumstance). If you rely on a post-par simulation to determine timing compliance, you are setting yourself up for a lot of grief down the line.

You will get more complete timing coverage by doing a proper timing analysis on the design. For synchronous designs, that is pretty easy to accomplish using the tools provided with all of the major FPGA place and route tools. The post-PAR simulation is really only useful for catching the very rare mistake by the PAR tools, or catching something that fell under a multi-cycle constraint when it didn't belong there.