Field-Programmable Gate Arrays

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synchronous clocks

I have a single input clock in my design, and it is used to drive clock enables to the entire design. The clock enables...
5 comments posted 20yrs
posted by szohair
5 comments posted 20yrs posted by szohair

Old vs. New FPGAs

I was updating a CPU design I did a few years ago and I was a bit disappointed in the results I see. The CPU was origin...
7 comments posted 20yrs
posted by gnuarm
7 comments posted 20yrs posted by gnuarm

Metastability resolution

I am designing a crossdomain synchroniser and wanted to check that I understand the formula for the mean time between m...
9 comments posted 20yrs
posted by comp.arch.fpga.posting.account
9 comments posted 20yrs posted by comp.arch.fpga.posting.account

Avnet LX25 Evaluation Board - USB Problems

Hi, I'm really struggling to get the Avnet LX25 Evaluation Boards USB port working. I have downloaded their USB Utility...
0 comments posted 20yrs
posted by alastairlynch
0 comments posted 20yrs posted by alastairlynch

Fixed-point FIR eyediagram problem

Hi, I am designing a fixed-point FIR using Xilinx block set.But it seems that only the upper half of the output eyediag...
2 comments posted 20yrs
posted by yifei.luo
2 comments posted 20yrs posted by yifei.luo

simulation mismatch (xilinx)

We are designing a comunication system on a Spartan3 with a lot of data processing and buffering. We have several simul...
2 comments posted 20yrs
posted by tullio.grassi
2 comments posted 20yrs posted by tullio.grassi

VHDL oddity

I would greatly appreciate if someone could explain the behavior I'm seeing for me. In the inner most if-state, where I...
8 comments posted 20yrs
posted by alexmchale
8 comments posted 20yrs posted by alexmchale

Ethernet MAC wrapper & ML403

Hello all, I am quite confused about the Ethernet MAC wrapper IP core. In the documentation is written (if I understand...
0 comments posted 20yrs
posted by misiu75
0 comments posted 20yrs posted by misiu75

Buffering the critical path.

Hello all, In my design i am using a 32 bit adder and some combinational logic after that. The full path i want to cons...
16 comments posted 20yrs
posted by vssumesh_asic
16 comments posted 20yrs posted by vssumesh_asic

Using a global clock as a flip-flop enable?

Hi all, I've heard that a good rule of thumb is to not to use a global clock as an enable for flops or RAMs. Even though...
2 comments posted 20yrs
posted by maverick1101
2 comments posted 20yrs posted by maverick1101

E1 to ethernet conversion

hi all, i'm doing a research about " E1 to Ethernet conversion" can any one suggest books or papers to read?? thanks
3 comments posted 20yrs
posted by en.sherine
3 comments posted 20yrs posted by en.sherine

uBlaze : -m compile directives...

Hi all. I'm using EDK 8.1.02i and I'm programming uBlaze. I have seen that related to uBlaze configuration (HW/SW FPU,...
3 comments posted 20yrs
posted by alfmyk
3 comments posted 20yrs posted by alfmyk

uBlaze : Reading Registers...

Hi all. I'm using ISE 8.1.03i EDK 8.1.02i I have found the header file "mb_interface.h" and it seems to be perfect for...
0 comments posted 20yrs
posted by alfmyk
0 comments posted 20yrs posted by alfmyk

Multiple External Interrupt handling in Microblaze

Hello. I am currently implementing a Microblaze system with 2 external interrupts. Let us call them bus_reset_INTR and...
0 comments posted 20yrs
posted by viswanathank
0 comments posted 20yrs posted by viswanathank