We are designing a comunication system on a Spartan3 with a lot of data processing and buffering. We have several simulation mismatches: behavioral simulation gives results identical to Post-translate (with XST8.2.02 and option Keep Hierarchy: yes) But simulation of Post-translate with XST and option Keep Hierarchy off, gives different results; it's only a few different vectors over a thousand, but still unexplicable to me. We tried to compile with Synplify Pro, default settings; we did another post-translate simulation and the results are still different from all previous cases (again only a few vectors over a thousand).
Any experience with that ? We paid attention to signed logic issues (see thread "behavioral vs post-P&R simulation mismatch" on Aug 30, 2006). We paid attention to crossing the clock domains. The clock structure is (in Verilog)
///////////////////////////////////////// ... input clk80, // 80 MHz clock. ... always @(posedge clk80) CE40