Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

xilinx fir ipcore

please tell me which one core is more suitable fot digital implementation , which are available in ISE. DA or MAC. Regar...
2 comments posted 20yrs
posted by jrgodara
2 comments posted 20yrs posted by jrgodara

XtremeDSP kit

Hi I'm planning to get the XtremeDSP kit with Virtex4 on it. http://www.xilinx.com/xlnx/xebiz/designResources/ip_produc...
0 comments posted 20yrs
posted by sutejok
0 comments posted 20yrs posted by sutejok

BUF component

How does a BUF component increase the drive strength of a signal? Thanks
1 comments posted 20yrs
posted by hpsham
1 comments posted 20yrs posted by hpsham

How to change coefficient word length

Hi, I am designing a FIR filter using Xilinx block set in MatLab. Could you tell me how to change the coefficient word...
0 comments posted 20yrs
posted by yifei.luo
0 comments posted 20yrs posted by yifei.luo

FPGA : Open core FFT

Hi all, Does any one used Open core FFT. I am trying to use it, but what my simulation results shows is that the perfor...
4 comments posted 20yrs
posted by pbijoy
4 comments posted 20yrs posted by pbijoy

regarding 4 bit multiplier

hi i need information regarding 4 bit multiplier
2 comments posted 20yrs
posted by kishoremi2
2 comments posted 20yrs posted by kishoremi2

Are you ready for Virtex-5? We are...

You can order Virtex-5 devices from your distributor now, and he will offer short delivery times. Whether the distribut...
35 comments posted 20yrs
posted by peter
35 comments posted 20yrs posted by peter

Xilinx xapp802.pdf mistake?

Mostly for xilinx people, xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes Available here: http:...
3 comments posted 20yrs
posted by dash
3 comments posted 20yrs posted by dash

Virtex4 Configuration ROM?

Just curious, does Virtex4 has its own built-in configuration ROM? as in it will automaticaly has the chip configured on...
4 comments posted 20yrs
posted by sutejok
4 comments posted 20yrs posted by sutejok

ddr clock issues

Open Cores DDR controller uses 2 DCM's to generate the clocks. clk -> dcm0 -> clock used for fddr to produce true + neg...
17 comments posted 20yrs
posted by dash
17 comments posted 20yrs posted by dash

Max Sample Rate using Signal Tap in Quartus 6.0?

Hello, I have a question concerning the maximum sample rate using Quartus' Signal Tap, I've heard that the maximum rate...
0 comments posted 20yrs
posted by jjlindula
0 comments posted 20yrs posted by jjlindula

Xilinx XAPP775: 10GbE PCS

Hello, Have anyone successfully implemented a working 10G Ethernet PCS in Virtex-II Pro devices using Xilinx XAPP775? I...
0 comments posted 20yrs
posted by markus_1401
0 comments posted 20yrs posted by markus_1401

Lattice ECP2/M

Cudos to lattice on the "inexpensive" SERDES and the plentiful memory! Serious contention for designs previously out of...
8 comments posted 20yrs
posted by newsgroup
8 comments posted 20yrs posted by newsgroup

how to do the synthesis

I am just finishing my verilog code on a project.And I am absolutely new to this field. And i got no clue how to do a s...
3 comments posted 20yrs
posted by windingson
3 comments posted 20yrs posted by windingson

Writing VHDL, Software dummy!

I have a couple of questions regarding VHDL and FPGAs as I am starting a project on them shortly0. Before I start I wou...
5 comments posted 20yrs
posted by chadland
5 comments posted 20yrs posted by chadland