Using a global clock as a flip-flop enable?

Don't do it man. Just don't. The delay from the clock signal leaving the global network to your flip flop is unknown and large. Hence it is impossible to syncronize your enable with your clock signal in that situation. There is no reason to do this. Post your circuit and we'll help you find a better way. I've thought that I needed this functionality in the past, but I've always found a way around it.

I have occasionally seen uses for driving the clock with logic rather than a global clock. This situation shows up in input IOBs or the JTAG connection lines.

mav1101 wrote:

It is better to create a signal which is a copy of the clock sampled by a clock which twice the original clock frequency.