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VHDL oddity

I would greatly appreciate if someone could explain the behavior I'm seeing for me.

In the inner most if-state, where I write to bDATA_OUT ---- if I run the program as written, it does nothing (my DATA_OUT lines remain in the state they were previously). If I remove the "else, bDATA_OUT

Reply to
Alex
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Hi Alex,

I modeled this with ISE 7.1 and ModelSimXE III 6.0d and the DATA_OUT alternates between 00001010 and 11000000 as I expected.

I am not sure what you expected to see.

Brad Smallridge aivision

Reply to
Brad Smallridge

Yes, I hadn't yet modeled it. It works fine in the simulator for me as well. The problem appears when I run it on our hardware. So now I'm left even more stumped.

Brad Smallridge wrote:

Reply to
Alex

You are scoping it? Or it's a video display?

It could be a rise time issue if the clock is too fast. That would explain how you see the "0001010" when you leave the else statement out.

Brad Smallridge aivision

Reply to
Brad Smallridge

Alex,

Couple of things strike me as cause for concern, being rusty on my VHDL I don't recall the semantics of incomplete specifications, ans would hesitate to say any of these comments will help, but still...

  1. if mode='0' clause does not define signals bDATA_OUT and column_out[].
  2. not sure why you have elsif mode='1' instead of just "else" -- synthesis is one thing but simulation considers 'X' 'U' 'Z' etc (9-value logic) and it's prudent to have "else" specified.
  3. synthesis and simulation may not implement logic identically.

HTH,

-rajeev-

Alex wrote:

Reply to
Rajeev

What clock rate is this running at? Is it meeting timing? Having the "if" might slow the circuit down.

Of course now that I think about it maybe not: tbit

Reply to
David Ashley

Alex, Its better to see your RTL shematic, anyway try this if it makes difference. Doubt if it is what you need :)

signal test std_logic; ... test

Reply to
Marlboro

Alex,

If I'm reading this correctly, it seems that column_out has no 'initial' state in HW. As far as I know, setting default values in signal declarations (i.e. what you've done) works fine in a simulator, but this information gets lost in synthesis, and thus HW (though there are ways around it via UCFs, etc.).

You are therefore trying to read a signal that hasn't been set to any state, and increment it by 1. Think of it as:

column_out

Reply to
michaelrbodnar

#1 is not an issue in a clocked process, only in a combinatorial process, where you could end up with a latch. In a clocked process, the incompletely specified values would have clock enables on the registers, that were disabled whenever they were not updated.

I write and use "is0()" and "is1()" functions (that return boolean) to correctly interpret metavalues such as 'H' & 'L', and assert warnings if other metavalues are encountered. They get optimized out in synthesis. Or I use integer, bit, or boolean types that don't have metavalues.

if is0(column_out(0)) then ... else ... end if;

Andy

Rajeev wrote:

Reply to
Andy

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