Hi,
I am designing a fixed-point FIR using Xilinx block set.But it seems that only the upper half of the output eyediagram ramains while the lower half has been truncated.In the design, I just use random integer Generator, then going through a Gateway In block, then upsampling block, then fixed-point FIR filer,Gateway Out block, AWGN block, Gateway In block, fixed-point FIR filter, downsampling, Gateway Out block and output display. Could anyone give me some suggestions about this eyediagram problem?
Thanks a lot!