Field-Programmable Gate Arrays

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Altera Avalon Bus VHDL stop error?

To all, I've develped a Master peripheral to connect to the Avalon Bus which interfaces a custom slave peripheral. The...
3 comments posted 20yrs
posted by pinod01
3 comments posted 20yrs posted by pinod01

Odd error in timing analyzer

I am trying to look at a failed timing path in the floorplanner and I expected to be able to click on a link in the tim...
1 comments posted 20yrs
posted by gnuarm
1 comments posted 20yrs posted by gnuarm

Generating PAD report very slow

Hello, I'm building a project with Xilinx ISE 8.2.02i. During "Implement Design" the process stalls for about 5 minutes...
0 comments posted 20yrs
posted by stuhrmann
0 comments posted 20yrs posted by stuhrmann

edk 8.2 user needed

hi i have a digilent spartan 3e board (rev. D) and i'm trying to get the ethernet going. i'm using microblaze/ethernetl...
4 comments posted 20yrs
posted by u_stadler
4 comments posted 20yrs posted by u_stadler

DCM virtex II pro

I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25 mhz clocks. I used DCM module but I get the foll...
3 comments posted 20yrs
posted by dhruvakshad
3 comments posted 20yrs posted by dhruvakshad

PCI Express

I am building a data input board that will have 1000/100/10 Base Ethernet, USB 2.0, IEE 1394, SATA, and a high speed ex...
4 comments posted 20yrs
posted by mdhicks2
4 comments posted 20yrs posted by mdhicks2

DCM for virtex II pro

I have a 25 mhz onboard clock. I need a 2.5mhz clock to be generated from it. I tried using DCM with CLk_DV value of 10...
1 comments posted 20yrs
posted by dhruvakshad
1 comments posted 20yrs posted by dhruvakshad

Xilinx OPB BFM simulation error with m_ABus signal

Hi, I'm developing a custom OPB master peripheral for Spartan3. I don't use IPIF. During simulation with BFM and Models...
1 comments posted 20yrs
posted by claudiolanconelli
1 comments posted 20yrs posted by claudiolanconelli

Help with webpack/ISE 8.2

Hi, I could use a bit of help with Webpack/ISE 8.2 from Xilinx. I am learning Verilog by constructing a small project i...
2 comments posted 20yrs
posted by nospam
2 comments posted 20yrs posted by nospam

uBlaze : Programming in C++... Is Possible ?

Hi all. Please, what are main steps to try programming in C++ on uBlaze ? It's mandatory use a XilKernel (little Kernel...
6 comments posted 20yrs
posted by Alfmyk
6 comments posted 20yrs posted by Alfmyk

Configuration of Cyclone devices

Newbie alert here... I'm trying to design a board that would allow me to configure a Cyclone device either through the...
0 comments posted 20yrs
posted by nevo_n
0 comments posted 20yrs posted by nevo_n

Spartan-3E USB for I/O?

I am new to FPGA and I can't find any info on this subject anywhere. Can the USB on the Spartan-3E be used for I/O at r...
7 comments posted 20yrs
posted by bob
7 comments posted 20yrs posted by bob