I could use a bit of help with Webpack/ISE 8.2 from Xilinx. I am learning Verilog by constructing a small project in it, in fact an 8080 CPU core.
I have completed the project, and am debugging it, but I can't seem to get the ISE 8.2 simulator to display signal traces down inside the module instantiations. After searches on this group's old messages, I gather that in older versions, 7.x and back, this was simply a matter of right clicking the signal in the signal names list and choosing the "add to wave" option. However, this does not appear to exist for 8.2, or was changed. I guess it is possible that the free webpack does not have that capability, but the Xilinx website seems to claim that the free version of the simulator "modelsim" is not limited in an way but speed.
Right now, the only way I appear to have to get signals out to the waveform pane is by routing them out to pins on my testbench, a tedious procedure at best.
Thanks in advance,