Field-Programmable Gate Arrays

How to create a library for a Xilinx project

Hi, I have a project that have many files generated by Xilinx CoreGenerator. Now I put all those vhdl files generated b...

6 comments posted 19yrs

posted by wtxwtx

6 comments posted 19yrs posted by wtxwtx

logarithm look-up table

Hi all, I'm about to convert the amplitude output from a Cordic to dB, 20*log(amp) that is. The output from the Cordic...

3 comments posted 19yrs

posted by xjohbex

3 comments posted 19yrs posted by xjohbex

JTAG cable @ 2.5 V - where?

Hi group I'm a newbee, so please bear with me if this does not make sense. I got a AVNet (MEMEC) Virtex 4 based develop...

5 comments posted 19yrs

posted by m.zingg

5 comments posted 19yrs posted by m.zingg

FPGA power-up and code relocation (basics)

Hi everybody, I'm a Ph.D. student on robotics and i'm *totally* new to the world of FPGA and i need little help underst...

7 comments posted 19yrs

posted by cispa

7 comments posted 19yrs posted by cispa

Virtex 4 Configuration Pins

When designing using a Virtex 4 (VCCO_0 = 3.3V) and a XCF16PV(VCCO=3.3V and VCCJ=3.3V) at MASTER-SERIAL connection the...

2 comments posted 19yrs

posted by tsalis

2 comments posted 19yrs posted by tsalis

Modules for IO on BSD indi processor ideas?

hi IO has been the thoughts of late. As all IO is from or to 1K x 16 bit words memory mapped buffers certain limits are...

5 comments posted 19yrs

posted by jackokring

5 comments posted 19yrs posted by jackokring

Looking for HDL code for sin( a ) and x ** y Functions

Before I get spamed for this I have done a search and I see there are references to what I'm looking for on www.opencor...

15 comments posted 19yrs

posted by dereks314

15 comments posted 19yrs posted by dereks314

Xilinx ISE 8.2 : Cannot find library

Hi, During synthesis, with Xilinx ISE 8.2 it seems it cannot find the library file I used: ERROR:HDLParsers:3317 - "......

0 comments posted 19yrs

posted by axr0284

0 comments posted 19yrs posted by axr0284

I2S serial to parallel conversion and generating C,V and Z bits

Hi, I'm working on interfacing I2S audio and am new at doing this. Could someone describe how I2S serial data (20-bit l...

3 comments posted 19yrs

posted by cbr_929rr

3 comments posted 19yrs posted by cbr_929rr

Net names from EDK => ISE

I have a Xilinx EDK based design for a Virtex II Pro using the PowerPC Processor. The PPC subsystem from EDK is a submo...

4 comments posted 19yrs

posted by sgfallows

4 comments posted 19yrs posted by sgfallows

Help with ISE WebPack 8.2i (moving project files)

Is there something I must do first before I copy or move a project to another place on my computer?

3 comments posted 19yrs

posted by gery

3 comments posted 19yrs posted by gery

LatticeMico32 extremly poor performance without caches

Hi just some results for LatticeMico32: * no cache * code and data in Block RAMs testing with software loop sw r0,r0,0x...

18 comments posted 19yrs

posted by Antti.Lukats

18 comments posted 19yrs posted by Antti.Lukats

EDK: Losing messages when using putfsl_interruptable together with getfsl_interruptable

Hi all, I discovered that I _lose messages_ when using an Fast Simplex Link (FSL) to transfer data from one MB to anoth...

1 comments posted 19yrs

posted by sputhnic

1 comments posted 19yrs posted by sputhnic

spartan 3E starter kit : usb/jtag write cmdbuffer failed

I am testing uclinux with microblaze (as explain in http://muranaka.info) on spartan 3E starter kit (digilent rev. D) a...

1 comments posted 19yrs

posted by rponsard

1 comments posted 19yrs posted by rponsard

Declaration of xilkernel_main()

Hi group, I'm currently developing a Communicating Sequential Processes library for the Xilinx Micro Kernel (XMK). I re...

2 comments posted 19yrs

posted by sputhnic

2 comments posted 19yrs posted by sputhnic