Field-Programmable Gate Arrays

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Declaration of xilkernel_main()

Hi group, I'm currently developing a Communicating Sequential Processes library for the Xilinx Micro Kernel (XMK). I re...
2 comments posted 20yrs
posted by sputhnic
2 comments posted 20yrs posted by sputhnic

PLB/OPB Bus Access from ISE

Is there an easy way to access the PLB or OPB buses from XIlinx ISE without going through the PowerPC and EDK? I am usi...
0 comments posted 20yrs
posted by akcooper8
0 comments posted 20yrs posted by akcooper8

using spartan 3E starter kit for CAN bus probe ?

Hi experts ! in your opinion, is it possible to build a CAN field bus probe (simple app. for edu. ; needs only to displ...
0 comments posted 20yrs
posted by rponsard
0 comments posted 20yrs posted by rponsard

System ACE woes

I'm trying to use the System ACE CF feature of the nice Xilinx ML401 board, but mysteriously, my .ace files doesn't wor...
9 comments posted 20yrs
posted by foobar
9 comments posted 20yrs posted by foobar

DDR RAM

Hi , i am new to the memory modules .I want to study about DDR Rams . So please send me the links to study in depth abou...
5 comments posted 20yrs
posted by vittal.patil
5 comments posted 20yrs posted by vittal.patil

Xilinx ISE 8.1i asks me to recover work?

Why does it often ask if I want to recover a schematic file from previous work when i open a schematic file?
0 comments posted 20yrs
posted by gery
0 comments posted 20yrs posted by gery

Little help needed with FT2232L USB demo board

Hi, I have hit a bottleneck while using FIFO interface mode of FTDI FT2232L USB demo board, which i plugged into my lin...
1 comments posted 20yrs
posted by men.r.fm.mars
1 comments posted 20yrs posted by men.r.fm.mars

Xilinx Virtex-2 Pro MUXCY does not drive local FF

Hi Folks When creating fast MUXes, I use AND/OR logic (sum of products, SOP) with the CYINIT and MUXCY to implement a 9...
3 comments posted 20yrs
posted by sphilipp
3 comments posted 20yrs posted by sphilipp

Filter trouble

Hi, I've generated a MAC-FIR Filter, using Xilinx' Core Generator (MAC FIR 5.1) from the Web Pack. The coefficients hav...
1 comments posted 20yrs
posted by tom.reinemann
1 comments posted 20yrs posted by tom.reinemann

Interfacing second bram port to user logic?

Hi all, I'm working on a Virtex-4 FX Design with a custom logic fabric and a PowerPC Core containing a dual port BRAM b...
5 comments posted 20yrs
posted by disentis
5 comments posted 20yrs posted by disentis

Help with xilinx OPB Arbiter

(EDK 8.1.02i) I have instantiated an OPB Bus/Arbiter around a microblaze wtih the following parameters: BEGIN opb_v20 P...
0 comments posted 20yrs
posted by me_zara
0 comments posted 20yrs posted by me_zara

ddr2 SODIMM controller - time simulation problem

I think the FIFO16 is not the killer of the simulation. i saw the empty flag and full flag toggle. I run the the synthe...
0 comments posted 20yrs
posted by waishanl
0 comments posted 20yrs posted by waishanl

state machine

I have a code which has 3 state machines .The code works fine. But if I add any other hardware to the design like adder...
1 comments posted 20yrs
posted by dhruvakshad
1 comments posted 20yrs posted by dhruvakshad

bit vs std_logic

Is there a good reason to use 'std_logic' by default rather than 'bit'? I started off doing so, then thought it would b...
4 comments posted 20yrs
posted by kryten_droid_obfusticator
4 comments posted 20yrs posted by kryten_droid_obfusticator