Modules for IO on BSD indi processor ideas?

hi

IO has been the thoughts of late. As all IO is from or to 1K x 16 bit words memory mapped buffers certain limits are placed on the devices

My current plans are PAL 1024 character display using 1 buffer, but would need a character ROM, or character bit map page. ascII 256 could be fitted into 1K x 16 bits as an 8 by 8 font, allowing five of the extra 16 bits in the character index to select a buffer page then 3 bits are left for character representing modifications i.e. eight colours.

A UART working at MIDI data rate for musical applications, along with translation software to provide an instrument control buffer i.e. easy variables for control wheel signals automatically modified by data stream.

A DAC 8 times oversampling delta sigma converter.again for musical applications which does 1K x16 bit buffer DMA output.

A minimal extra parts needed ADC based on the DAC with fixed size buffer DMA.

A bit reversal load store memory cell for FFT indexing. which may be extended to do auto FFT and programable hardware biquad chains.

A USB controller/ slave mode too.

A display and keypad scan multiplex controller.

A data compression codec.

what else would people require in terms of modular cores?

cheers.

Reply to
jacko
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jacko schrieb:

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you are not doing the things in right order IMHO

1) Arch description 2) HDL testbench or fixture 3) toolchain + assembler compiler tests 4) onchip bus infrastructure

only when the above is finalized then there the peripherals make sense, unless the cores is working verified and supported by tested software tools, the existance (or lack of) peripherals makes absolutly no difference.

Antti

Reply to
Antti

Read the ISA and look at the circuit this early in the project.

this will be the FORTH ROM and a modified FORTH-83 test suite.

The operation of the base vocabularies will depend quite a lot on the utility to which the design will be put.

it will be avalon or wishbone, when i end up needing to use the on chip bus for a first product development.

i like to see where i'm headed, as well as where i am due to the direction to head in is controlled by the final destination. the pheripheral IO is on the agenda at the moment as this will decide the high level structure of the API. I could do things to an order, but i see no pink slips paying the bills, so i'll have to run it the way i see it in the eye of the mind.

i was thinking of a track loop phosphorus-arsnic NMR factorizer by gussian sum, but not now, but it may relate to the HAL generics.

cheers

Reply to
jacko

"jacko" schrieb im Newsbeitrag news: snipped-for-privacy@m73g2000cwd.googlegroups.com...

I have. plenty many unknowns processor states? special registers? interrupts? exceptions? addressing ranges for diferent address spaces?

all only open questions!

anything that contains 'will be' means nothing. it either is or is not available.

hm - sorry by toolchain I did mean C compiler of course. nobofy wants forth unfortunatly.

yes, I have programmed in forth back then when 80286 based machines did come out. I have even developed a single chip based computer based on PIC16F84 where forth like interpreter and interactive monitor editor all was fitted into 512 word ROM.

but - there are plenty of forth FPGA CPU's available, and there seems to ZERO interest.

now Java VM is actually a forth engine, but guess what? Sun is not offering forth as front end for their forth enginge, no Java language is something totally different (the forth VM is hidden from the user)

so unless you have a C compiler front end, there will be equally zero interest to your processor as it zero interest to other currently available forth FPGA CPU's.

your total earnings from the project are estimated to be i was thinking of a track loop phosphorus-arsnic NMR factorizer by

?!

Sorry Jon if I sound like fun-killer to you. I am just giving my 2 cents.

cheers Antti

Reply to
Antti Lukats

1 pin to select user or super mode registers.

none as yet

no interrupt controller yet, would be part of the pheriph devices, which toggles user super register set.

no none of this either. but may be detected by user logic to toggle super/user pin.

16 bit address (or 32 if two joined, or 64 if 4 joined) and 2 bits to indicate which address register is used, and a fetch pin to indicate insruction fetch cycle.

not yet available, wordlist.mdb in the project directory is the current state of word defininitions and word documentation.

no C compiler yet, and java may be more likely. although of course the full sun library will not be supplied.

ok

i'm interseted, so i will develop and release things as they become needed for the first project using the indi.

makes a good native language for java if you ask me, but then people love the C code base. although c to forth translator does exist.

the cpu is not necessarily forth, i'm just doing forth. it's a flat address space cpu which runs a machine code with 4 (source and dest =

2-operand) instructions.

i think i will have to design my own project first. on which i aim to make mony, after first product design, much more will be available for a user base.

formatting link

and NMR needs odd number of protons.

ok. i can take constructive critisism, and i am sure C will be done by someone some day, as the instruction set is very simple to emulate. but it wont be me today, as i have other things in the pipeline, and out of order execution is not yet available within the indi design.

biggest selling point is arround 700 LEs and uses no BRAM or other resources for microcode and the like. to use it as a 16 bit just join the caryy out to the carry in, and connect your own level based interrupt source to the super/user pin. user the address and data bus to connect to 64K x16 bit words of RAM.

cheers

Reply to
jacko

and also the CAIN has to be connect to vcc to make address generation post pre inc/dec work, and the CAOUT can be chained to multiple indi16s to get 32 48 and 64 bit.

when using 32, 48 or 64 the fetch signal can be used to direct the program opcode into all indi16 cpu units. any questions??

Reply to
jacko

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