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Net names from EDK => ISE

I have a Xilinx EDK based design for a Virtex II Pro using the PowerPC Processor. The PPC subsystem from EDK is a submodule of an ISE based schematic design. There are about 7 cores around the PPC and all was working fine. Then I added a second GPIO for some input lines and it won't run at all anymore.

So, I want to add some timing constraints for the clocks. However when I do so ISE complains; I added these lines to the UCF file:

NET "sys_clk_s" TNM_NET = "sys_clk_s"; TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" 10 ns HIGH 5;

ISE says it can't find sys_clk_s in the design.

So I tried these variations of the net name (PPD_DDR is the EDK project name):

PPC_DDR/sys_clk_s PPC_DDR\sys_clk_s

PPC_DDR_stub/sys_clk_s PPC_DDR_stub\sys_clk_s

all with the same result.

How am I supposed to refer to a net in the EDK design in the ISE .ucf file?

Reply to
Steve
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Instead of editing the UCF manually open the constraints editor, or open the design in FPGA editor and you will be able to see the proper hierarchy and net names. Your clock probably iriginates in the ISE portion of the design where it is most likely called differently. The clocks are always constrained as close to the source as possible.

/Mikhail

Reply to
MM

Thanks for the reply. The clock I was thinking of constraining, is the PLB and OPB clock in the EDK design. It is generated by a DCM in the EDK design, multiplied up from 10 MHz to 100 MHz. Your answer made me realize I should put a (period) constraint on the 10 MHz clock.

My question now is, will a constraint on a DCM input clock "propagate through" the DCM and create a period constraint on the generated clock(s)?

Reply to
Steve

Thanks for the reply. The clock I was thinking of constraining, is the PLB and OPB clock in the EDK design. It is generated by a DCM in the EDK design, multiplied up from 10 MHz to 100 MHz. Your answer made me realize I should put a (period) constraint on the 10 MHz clock.

My question now is, will a constraint on a DCM input clock "propagate through" the DCM and create a period constraint on the generated clock(s)?

Reply to
Steve

Reply to
Steve

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