Hi,
Virtex-4 has many new things, one of them is access to CCLK as output after configuration. CCLK control is required to readback data from XCF devices, this approuch is described in Xilinx Application note XAPP482. Until today I did live in believe that this was the reason why startup primitive was modified in Virtex-4, but today I was about to check the pinout for XCF data read able design, and uuuuups - CCLK access is added in Virtex-4 but at the same time input access to DIN has been removed!? Or at least I cant see how to read the DIN pin from FPGA fabric. So if for Spartan-3 the XAPP482 solution suggested a FPGA I/O pin to be routed parallel to CCLK, then well this wire is not required in Virtex-4, but now we need another FPGA I/O to be routed to DIN because DIN is no longer accessible?
I cant belive this to be true ! But I also fail to see any other solution for XCF data read with Virtex-4. Of course a solution would be using Virtex-5 where the DIN is again made accessible with the modified again STARTUP primitive.
I am too glad that I did not trust me belives that the CCLK fix in the Virtex-4 fixed the additional wiring requirement as per XAPP482 and checked the design before submitting to PCB fabrication.
I wish Xilinx would update XAPP482 with wiring diagram for all families. The DIN no access thing was really an almost unbelivable surprise for me :(
Antti