Field-Programmable Gate Arrays

Xilinx coregen fifo

I generated a fifo with block rams with two independent clocks and a symmetric widths and depths. the fifo manual digra...

3 comments posted 19yrs

posted by nbg2006

3 comments posted 19yrs posted by nbg2006

EDK Bug

hi i hav a problem with edk. i created a poject a while ago and everything worked fine. but today i changed some c code...

11 comments posted 19yrs

posted by u_stadler

11 comments posted 19yrs posted by u_stadler

ML501 finally released

I'm surprised none have mentioned it, but the Xilinx ML501 has finally been released officially, even though it's not a...

2 comments posted 19yrs

posted by tommy.thorn

2 comments posted 19yrs posted by tommy.thorn

Virtex-4 configuration details

Hello, I'm currently looking at the virtex-4 configuration details and have a question about FDRI writes in the virtex4...

0 comments posted 19yrs

posted by jbnote

0 comments posted 19yrs posted by jbnote

Nios software IDE

Hi, I am trying to create a project within the nios software ide (which is based on eclipse). I want to have my project...

5 comments posted 19yrs

posted by someone

5 comments posted 19yrs posted by someone

boundary scan

I know about the bscan blocks in the xilinx virtex devices (bscan_virtex4 for instance). With these blocks you can make...

3 comments posted 19yrs

posted by someone

3 comments posted 19yrs posted by someone

SDRAM initialisation and MCF5272

Hi, According to the MCF5272 datasheet, and the schematic, the address line A22 and A23 of ColdFire are to be treated a...

0 comments posted 19yrs

posted by karthik.balaguru

0 comments posted 19yrs posted by karthik.balaguru

longest webcase record

All I am wondering what the record is for having the longest Xilinx webcase open . All I asked was whether I can do bou...

33 comments posted 19yrs

posted by colin_toogood

33 comments posted 19yrs posted by colin_toogood

Finite State Machine

Hi, Do you think that it is a good idea to control several blocks of the design (for example with a 802.11 transceiver)...

1 comments posted 19yrs

posted by jmunir

1 comments posted 19yrs posted by jmunir

CPLD's and labels

OK -- our old label maker is on the fritz and parts are no longer available.... Does anybody make a label sized for PAL...

3 comments posted 19yrs

posted by See_my_website_for_email

3 comments posted 19yrs posted by See_my_website_for_email

FPGA and ZBT/NoBL SRAM timing issue

Greetings comp.arch.fpga group, I am having some trouble implementing a ZBT or NoBL SRAM interface. I am using a Xilinx...

3 comments posted 19yrs

posted by bradsmallridge

3 comments posted 19yrs posted by bradsmallridge

FPGA to SRAM port interface

I'm interfacing an FPGA to a multiplexed SRAM port (ALE, READ, WRITE, DATA/ADDR bus). I want to read from/write to the...

20 comments posted 19yrs

posted by oen_no_spam

20 comments posted 19yrs posted by oen_no_spam

Virtex 4 SX, Dedicated Configuration pins

Hi eveyone, I am designing a schematic for a project using Virtex-4 35 SX, and a platform flash for configuration (XCF1...

1 comments posted 19yrs

posted by tsalis

1 comments posted 19yrs posted by tsalis

Control of physical layer in a 802.11b

Hi, I am developing the physical layer of one 802.11b transceiver, I have designed the DBPSK, DQPSK, CCK modulators, sc...

0 comments posted 19yrs

posted by jmunir

0 comments posted 19yrs posted by jmunir

ISE/EDK computer selection

Hi all, I am buying a new for my work. I do a lot of synhesis, map and P&R using ISE 8.2 (Windows) in Xilinx EDK with q...

5 comments posted 19yrs

posted by ales.gorkic

5 comments posted 19yrs posted by ales.gorkic