EDK speed optimisation

in an EDK project, is it possible (as with ISE) to verify vhdl syntax of one file, before a long long make that abort complaining that syntax of a user_logic.vhdl is missing some ; or ' ...

batch compilation would be a must

Reply to
rponsard
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snipped-for-privacy@gmail.com schrieb:

you can setup and ISE project or batch file for this there is IMHO no other solution at the moment

Antti

Reply to
Antti

You can place your user designed logic at the top of the .mhs file. In this case it is the first block which is synthesized.

Frank

Reply to
Frank van Eijkelenburg

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