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Virtex 4 RAMB16 Clock: optional inverter missing

Hello,

The RAMB16 component has much less clock-to-out time when using the optional output register. However, I need valid data one clock cycle after the address input is valid.

The Virtex-4 User Guide ug070 states in Figure 4-5 (Page 115) that there are two optional inverters in the clock path. Also the port signal description (pg. 119): CLK polarity is configurable.

I wanted to enable both inverters. The RAM content should than be clocked out at the falling edge. And the register delivers data at the following rising edge.

Problem: There are only generic parameters to enable the clock inverter at the output register: INVERT_CLK_DO[A|B]_REG

Does anyone know how I can adjust the clock polarity (without using the DCM CLK180 output)?

Thanks

Frank

Reply to
Frank Leischnig
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Do you explicitly have a problem if you invert the clock in your source code?

Reply to
John_H

Do you mean something like:

clk_n clk_n, ... );

Will this be implemented into the "optional inverter" or into slice? I would not like it if the implement tools complain about "gated clocks", but as far as it works reliable I have no problem with this solution.

I'll try it.

Thanks

Frank

Reply to
Frank Leischnig

Frank Leischnig wrote

This saves a bit of typing/declaration stuff:

clkb => "not"(clk),

Reply to
Tim

Hi Frank - As John/Tim said this should work. The Software knows about the optional inverter and will use them.

If you want to doublecheck - you can use fpga_editor (to open your ncd) to zoom in on that particular BRAM instance - double click on the BRAM and look at the clock connections and attribute settings on the BRAM.

- Vic

Reply to
Vic Vadi

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