Hi,
With all this talk of sync resets, I was curious:
- If you apply reset async and de-assert sync, does this signal automatically get distributed using the FPGA's global reset resources (GSR for Xilinx, Global for Altera)? Are there any hidden gremlins with this technique (aside from not filtering glitches on the reset input pin) ?
- Do all modern FPGAs have flops with synchronous reset inputs? Or does it even matter? I'm thinking in the case of a purely synchronous reset, you might want to avoid any nebulousness by NOT using the async reset, even if your reset signal is fully synchronized.
John.