Field-Programmable Gate Arrays

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Help with SysAce CF

Hi All, I've been trying to work with a Xilinx II Virtex Pro board and its SysAce controller. I've read many papers and...
0 comments posted 20yrs
posted by psbthegr8
0 comments posted 20yrs posted by psbthegr8

Can I unstantiate IBERT core in a V4FX design?

I know the documentation says I can't do it, however looking at the files generated by the Chipscope Pro Core Generator...
0 comments posted 20yrs
posted by mbmsv
0 comments posted 20yrs posted by mbmsv

S3ESK JTAG

Hi all, Did anyone try to use the Spartan3 Starter Kit (S3ESK) as a USB JTAG programmer? I want to connect the Virtex4...
0 comments posted 20yrs
posted by ales.gorkic
0 comments posted 20yrs posted by ales.gorkic

Avnet virtex-5 board

Avnet is also now selling V5 eval kit AES-XLX-V5LX-EVL50 http://www.em.avnet.com/ctf_shared/evk/df2df2usa/xlx_v5_lx_dev...
0 comments posted 20yrs
posted by Antti.Lukats
0 comments posted 20yrs posted by Antti.Lukats

Memory

Hi I am writing a memory controller for a zbt sram. Do I need to be concerne with the setup times. What I mean by this...
2 comments posted 20yrs
posted by maxascent
2 comments posted 20yrs posted by maxascent

Please Help

Hi all, I have done a project in which FPGA implementation is done.I have used Xilinx7.1i FPGA tool. I have written cod...
3 comments posted 20yrs
posted by raghujindia
3 comments posted 20yrs posted by raghujindia

ISE 8.2 freeze

is that a known bug ? ISE 8.2 / win XP seems to freeze while synthesing design (no more mouse or menu/button action eve...
4 comments posted 20yrs
posted by rponsard
4 comments posted 20yrs posted by rponsard

microblaze uclinux ping delay

Hi all, I'm evaluating the porting of uclinux on microblaze. now I'm performing a ping between a laptop PC and microbla...
1 comments posted 20yrs
posted by francesco.poderico
1 comments posted 20yrs posted by francesco.poderico

DDR SDRAM access with MPMC2, Databus Width

Hi all, I'm working on a Virtex-4 FX12LC Design with PPC405 Core, SDRAM and Multiport Memory Controller 2 (MPMC2 releas...
6 comments posted 20yrs
posted by disentis
6 comments posted 20yrs posted by disentis

Memory Replicator

I have design in which, all the data will be stored in memory (Buffer). For that design i am writing a test document in...
0 comments posted 20yrs
posted by pjsenthil
0 comments posted 20yrs posted by pjsenthil

Xilinx Virtex4 DDR clock output

How do you set up a differential DDR output clock? In the Spartans there was a DDR register where you would tie one dat...
7 comments posted 20yrs
posted by bradsmallridge
7 comments posted 20yrs posted by bradsmallridge

Data2Mem Error Help on dual PPC system

Hello, I'm having a problem when Data2Mem runs and was wondering if someone could help me out. I have a simple dual PPC...
2 comments posted 20yrs
posted by HEEEY.STEVE
2 comments posted 20yrs posted by HEEEY.STEVE

Survey on Quartus SOPC/Nios-II

I am evaluating using the Altera Cyclone with Quartus SOPC vs. Xilinx Spartan3E and PicoBlaze. I need a soft core proce...
25 comments posted 20yrs
posted by nospam
25 comments posted 20yrs posted by nospam

How to check if ROM got inferred from synth reports

Hello. I have been trying to write code that should infer a ROM using Block RAMs. The target device is spartan II serie...
3 comments posted 20yrs
posted by aijazbaig1
3 comments posted 20yrs posted by aijazbaig1