Xilinx Virtex4 DDR clock output

Well, you "could" but, the old spartan method works fine. You can also use only one output DDR flip flop connected to a OBUFDS that will output a differential signal on two pins.

Sylvain

Sylvain Munaut schrieb:

Sylvain

what you wrote is an 'uups' ?

most DDR memory do not use differential signalling?

Antti

The OP question was "How do you set up a differential DDR output clock?" So I guessed what he wanted to do is send the clock from the FPGA to the DDR, using the internal clock driving a DDR IOB flip flop.

And most DDR chips have a differential clock, so either you use two DDR flip flops with inverted inputs, or a single one and a differential iob driver.

Sylvain

Here's a Verilog implementation to output my PClk (Virtex 4):

ODDR pclkff(.Q(PClkO), .C(PClk), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(1'b0), .S(1'b0)); OBUFDS pclk0 (.O(PClkOP), .OB(PClkON), .I(PClkO));

I assign the IO attributes in the .ucf

I guess my confusion is that when you go to the FPGA Editor one sees an OSERDES box near the output pin and not the set of registers you see in a Spartan.

This is a differential output for an xclk Camera Link interface, if that matters. Not a memory device.

Brad Smallridge aivision

Sylvain Munaut schrieb:

uups I need a vaccation.

clk pins are different story, I missed that in oringal post

Antti

You may still instantiate an ODDR primitive followed by an OBUFDS. The OSERDES is a superset of ODDR, so instantiating the ODDR will set up the OSERDES as an ODDR.

-Kevin