How to check if ROM got inferred from synth reports

Hello. I have been trying to write code that should infer a ROM using Block RAMs. The target device is spartan II series FPGA. I have come up with the following code which does get synthesized properly and also gets synthsized. But i wonder if I have been able to acheive my objective of realising ROMs using block RAM as the synthesis report never shows anything that any block RAM was ever used.

Heres the code:

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; USE ieee.std_logic_unsigned.all;

ENTITY BLOCKROM_Coeffs IS PORT( clk : IN std_logic; reset : IN std_logic; en : IN std_logic; addr : IN std_logic_vector(7 downto 0); data : OUT std_logic_vector(15 downto 0) );

-- Declarations



type rom_type is array(255 downto 0) of std_logic_vector(15 downto 0); constant ROM : rom_type:=(others=>X"0000"); attribute rom_extract : string; attribute rom_style : string; attribute rom_extract of ROM : constant is "yes"; attribute rom_style of ROM : constant is "auto";

BEGIN process(clk) begin if (clk'event and clk = '1') then if (en = '1') then data

Reply to
Loading thread data ...


I don't think there's anything wrong with your template for inferring the rom in block ram. I don't even think you will require the attributes you added, though I doubt they hurt. I think the problem is simply that the rom contents you specified are all zero, therefore the synthesizer optimises all this logic to a constant and removes it.

Both methods work fine. Using RAM inferred from HDL is my preferred solution when ever possible. Doing so leads to faster simulation and generic code that applies equally to various different FPGAs (both in terms of vendors and families).

On the other hand you cannot always infer a RAM which covers all the many features of, say, a Xilinx a block RAM from HDL code so on occasion it is necessary to get down and dirty and instantiate them yourself.

I cant say I have ever needed the feature, but that may well be the case. The libraries guide should tell you all you need to know.



Reply to
Andy Ray

It used to be that simulators required ROM content as generics, & the synthesiser (XST, anyway) needed the same data as attributes. I believe (haven't tried) that the latest XST can read the data from an external file, using standard VHDL statements which any simulator will accept. (Of course, 3rd-party synthesisers probably can't do this: reading a file is generally not synthesisable). I had a project some time back that ran into this: it was a royal PITA. I ended up writing a perl script to generate code for this & several other artifacts (PLA's, etc.)

Reply to
David R Brooks

IIRC, it's the mapper that actually instantiates the block RAM.

If in doubt, call up your design in the 'fpga editor' (view/edit routed design) and look for wires connected to the RAM blocks.


Guy_Sweden wrote:

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.