Hello. I have been trying to write code that should infer a ROM using Block RAMs. The target device is spartan II series FPGA. I have come up with the following code which does get synthesized properly and also gets synthsized. But i wonder if I have been able to acheive my objective of realising ROMs using block RAM as the synthesis report never shows anything that any block RAM was ever used.
Heres the code:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.numeric_std.all; USE ieee.std_logic_unsigned.all;
ENTITY BLOCKROM_Coeffs IS PORT( clk : IN std_logic; reset : IN std_logic; en : IN std_logic; addr : IN std_logic_vector(7 downto 0); data : OUT std_logic_vector(15 downto 0) );
END ENTITY BLOCKROM_Coeffs ;
-- ARCHITECTURE blkram_ROM OF BLOCKROM_Coeffs IS
type rom_type is array(255 downto 0) of std_logic_vector(15 downto 0); constant ROM : rom_type:=(others=>X"0000"); attribute rom_extract : string; attribute rom_style : string; attribute rom_extract of ROM : constant is "yes"; attribute rom_style of ROM : constant is "auto";
BEGIN process(clk) begin if (clk'event and clk = '1') then if (en = '1') then data