Field-Programmable Gate Arrays

EDK 8.2i/cygwin issues

Dear all, I am new to the EDK and just trying out my first project. I am running EDK 8.2i on Windows XP . I already hav...

4 comments posted 19yrs

posted by petermendham

4 comments posted 19yrs posted by petermendham

maximum distanse beetwin SFP-module and FPGA (RocketIO) ???

If this distanse is 70 mm may I hope that the devise is work correctly? And may I do not connect terminate resistor beet...

8 comments posted 19yrs

posted by axalay

8 comments posted 19yrs posted by axalay

Conformal compare retiming netlist and RTL

Hi all, I use conformal to compare logic with netlist and RTL. But some logic is synthesized by retiming. Can I set som...

0 comments posted 19yrs

posted by zhushenli

0 comments posted 19yrs posted by zhushenli

SystemVerilog not use Mail-box directly in VMM and AVM ?

Hi all, I was told that transaction layer communication is the very important thing in SystemVerilog testbench construc...

7 comments posted 19yrs

posted by zhushenli

7 comments posted 19yrs posted by zhushenli

JTAG connection for chipscope

Hi, I need help for solving the following problem.I am trying to connect to ML461 JTAG port from PC parallel port by us...

5 comments posted 19yrs

posted by kollarameshk

5 comments posted 19yrs posted by kollarameshk

digilent spartan-3 board sram timing

Hi, This is a question about digilent spartan-3 starter board , which has a simple 10ns sram and 20ns clock. I am using...

3 comments posted 19yrs

posted by anon-bounces

3 comments posted 19yrs posted by anon-bounces

Scientific Computing on FPGA

Hi, Coming from a scientific computing standpoint (with no hardware experience). I was wondering if you can improve any...

33 comments posted 19yrs

posted by lancepickens

33 comments posted 19yrs posted by lancepickens

chipscope

I am trying to use Xilinx chipscope, but it is not working properly (probably mishandling by the user...). Perhaps some...

4 comments posted 19yrs

posted by r.mattos

4 comments posted 19yrs posted by r.mattos

reset

I am using Altera Stratix II FPGA and also power supervisor circuit which generates reset which it tied to nCONFIG for...

14 comments posted 19yrs

posted by martstev

14 comments posted 19yrs posted by martstev

EDK software development

I'm writing a software for microblaze soft processor (Spartan 3E Starter Kit) and I have a few questions regarding the...

2 comments posted 19yrs

posted by eejju

2 comments posted 19yrs posted by eejju

How to avoid negative slack?

Hi, I am facing negative slack issue in timing analysis. The timing analysis report is as foolows: From: BufferFul2:CLK...

6 comments posted 19yrs

posted by himassk

6 comments posted 19yrs posted by himassk

Aurora v2.5 for V4FX - No "channel_up" in post-routed simulation during 200 us

Hi! I built aurora core 2.5 (32 bit, 1 lane, stream) for v4fx60. Behaviorial simulation of ref desing is ok. But when I...

2 comments posted 19yrs

posted by s.checkrygin

2 comments posted 19yrs posted by s.checkrygin

Warning LIT:176, DCM in Virtex 4?

I'm receiving a strange warning in ISE for a Virtex 4. I've been seeing new warnings and infos using the new DCMs. Is i...

2 comments posted 19yrs

posted by killerhertz

2 comments posted 19yrs posted by killerhertz

I can not simulate "pipelined divider v3.0"

Hello, I can not simulate "pipelined divider v3.0" .My verilog code is below: `timescale 1ns / 1ps module divide(divide...

1 comments posted 19yrs

posted by hikmetkoca

1 comments posted 19yrs posted by hikmetkoca

Quartus synthesising out signals?

Hi all, We had some strange behaviour with our project today. We have been using Mentor Graphics HDL Maker, ModelSim an...

1 comments posted 19yrs

posted by joel.pigdon

1 comments posted 19yrs posted by joel.pigdon