EDK software development

I'm writing a software for microblaze soft processor (Spartan 3E Starter Kit) and I have a few questions regarding the using of memory.

The first question is where my code is running? The starter kit has an external 64MB DDR memory and internal local memory (Use BRAM). When I download the bit stream to the FPGA, where is the program running? It seems it is running in the local memory.

Since the local memory is not big enough, for large size elf it should be running inside the DDR. I faced the error "region ilmb_cntlr_dlmb_cntlr is full" and I guess it's caused by the samll size local memory. Can anybody tell me how I can make my program run from the DDR? Do I need to develop a BSP for that?

Normally the tutorial tell us the "Mark to Initialize BRAMs", that why I guess the code is downloaded to the BRAM instead of the external DDR. What's the real meanning behind this step?

It seems the only method to update the code on FPGA is re-download the bit stream file. However, since the hardware has been fixed and we don't change the hardware much, is there a method that we can only update the software part without touching the whole bit file?

Thanks a lot.


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You can update the bitstream by simply recompiling your project, and then running "Device Configuration -> Update_Bitstream" (or clicking the BRAM INIT button). This will update the contents of the BRAM's. However, if your application is so large that it won't fit in internal memory, this won't do much.

Note, you can tell where your code is located by running the generate linker script on the project you are interested in. If your code is located in an external memory, you will need to use XMD to load it for debugging.

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Hi Steve,

The microblaze will boot from the memory mapped at address 0x00000000 (reset vector). This is usually an internal RAM block connected to an LMB controller on the ILMB, but it could be something else.

Note that the memory mapped at address 0x00000000 must be initialised before starting the processor. If you want to map the DDR at the reset vector, you will need to initialise memory externally (using XDM when debugging for instance, or dedicated logic in the FPGA).

Another solution would be to write a small boot loader that will be loaded in the internal BRAM by the bitstream. The boot loader will fetch the main software from a bigger memory (this could be a serial or parallel flash), write it to DDR and jump in external RAM. The boot loader must be compiled to run from the internal BRAM, and the main software from DDR.

Like radarman mentioned, you can update the bitstream without recompiling the whole FPGA, either through "Device Configuration -> Update_Bitstream" or with the "bitinit" command line software.

Hope this helps.

Laurent Pinchart

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Laurent Pinchart

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