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Warning LIT:176, DCM in Virtex 4?

I'm receiving a strange warning in ISE for a Virtex 4. I've been seeing new warnings and infos using the new DCMs. Is it safe to ignore this warning in MAP? I couldn't find anything related in the knowledge base. This autocal appears to be generated for speed improvement?

Help is much appreciated.

Thanks,

-Brandon

WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol "clkgen_inst/usrclk_dcm_clk0_bufg_inst" (output signal=clkgen_inst/usrclk) has a mix of clock and non-clock loads. The non-clock loads are: Pin I0 of

DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m d/_n00001 Pin I1 of

DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/m d/_n00011

Reply to
Brandon Jasionowski
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I'm also receiving this similar warning:

WARNING:PhysDesignRules:372 - Gated clock. Clock net

DCM_AUTOCALIBRATION_clkgen_inst/usrclk_dcm_inst/clkgen_inst/usrclk_dcm_inst/C LKOUT is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

Brand> I'm receiving a strange warning in ISE for a Virtex 4. I've been seeing

Reply to
Brandon Jasionowski

Refer to the following -

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HTH.

Reply to
VC

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