SystemVerilog not use Mail-box directly in VMM and AVM ?

Hi Davy

I can't speak for the VMM, but the AVM does use SystemVerilog mailboxes at the heart of its tlm communication.

The reason this is not obvious to the user is because the AVM channels (eg tlm_fifo) provide additional functionality over a pure mailbox, with multiple communication interfaces (put, get, peek, blocking, non-blocking ...) and analysis ports to send any transaction written/read to/from the channel to any registered analysis components (scoreboards, coverage collectors ...)

If you've downloaded the AVM

have a look at utilities/systemverilog/avm/tlm/tlm_fifos.svh for the detailed code and you'll see the mailbox construct.

Also, the AVM's use of virtual interfaces is not related to tlm communication. The virtual interface is the mechanism used to link the class based verification environment to the module based dut. Generally this is connecting a pin-level transactor (with a virtual interface) to an actual interface on the dut.

Hope this helps

regards

- Nigel

Hi NigelE,

Thanks a lot! I mis-understand virtual interface.

Is there any web seminar or online video talk about AVM? That I want to understand AVM more clearly.

Best regards, Davy

NigelE wrote:

Hi Davy

Try a look at

You'll find listed in the online events, our recent 'Hitchhikers Guide to Verification' seminar that covers AVM and other SV verification topics.

It's split into 5 sessions so you don't need to watch it all at once ;)

Best regards

- Nigel

Hi Nigel,

Thanks a lot for the help!

Best regards, Davy

The direct path to 'Hitchhikers Guide to Verification' seminar is

Just a memo for myself :)

Thanks! Davy

Hi NigelE,

Is AVM IEEE 1800 compatible? Thanks!

Thanks! Davy

NigelE wrote:

Yes it is.

Adam.

Adam Rose Verification Technologist Mentor Graphics