This is a question about digilent spartan-3 starter board , which has a simple 10ns sram and 20ns clock. I am using a simple controller to access the sram. During a read operation, the address is stored into a register and oe is activated at the first rising edge of the clock and data is retrieved at the next edge. The 20 ns period seems not large enough to accommodate the pad delay and external loading. A simple testing circuit shows that about 0.2% read errors. There is no error if the reading period is extended to 2 clocks.
Is it possible to put some timing or other constraints in the ucf file to help timing? Thanks.