Field-Programmable Gate Arrays

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SDRAM of Spartan 3E

Hi, I am new on FPGA. I am planning to buy a spartan3e starter kit. But I don't have idea if it has enough resource for...
1 comments posted 19yrs
posted by Johnathn
1 comments posted 19yrs posted by Johnathn

EDK post 7.1 Opinions

I was just wondering what others thought about the 'New 8.X' EDK. Three people in my group at work have used the EDK si...
0 comments posted 19yrs
posted by mottoblatto
0 comments posted 19yrs posted by mottoblatto

Virtex-5 Webpack?

Hello! For a long time my lab purchased the lower-cost ISE Base-X kit, which was recently discontinued and its function...
14 comments posted 19yrs
posted by jonas
14 comments posted 19yrs posted by jonas

replacement for Altera EPCS64

Hi, Altera EPCS64 is a 64Mbit serial flash memory used for AS configuration in SOIC16 package. The SOIC package is too...
0 comments posted 19yrs
posted by piclist9
0 comments posted 19yrs posted by piclist9

MPMC2 with Virtex-5

Hi I wonder if the MPMC2 system can work on Virtex-5, the last release of MPMC2 does generate a UCF file that matches X...
0 comments posted 19yrs
posted by antti
0 comments posted 19yrs posted by antti

Xilinx Chipscope and EDK

I just used Xilinx Chipscope with EDK for the first time and it is great! Just drap and drop chipscope_icon and chipsco...
1 comments posted 19yrs
posted by alan
1 comments posted 19yrs posted by alan

"|->" implicate and sequence in SVA?

Hi all, I have two problem of SystemVerilog Assertion. About property implication and sequence. 1. Is //-------- proper...
3 comments posted 19yrs
posted by zhushenli
3 comments posted 19yrs posted by zhushenli

Quartus download problem?

I am a newbie with this FPGA stuff, but I'm having to use a Stratix II design to develop some software until they can g...
0 comments posted 19yrs
posted by druffer
0 comments posted 19yrs posted by druffer

using FPGAs for synthesizing?

I was reading about the multi processor support in upcoming Quartus software and I wonder if another idea to increase s...
2 comments posted 19yrs
posted by fb
2 comments posted 19yrs posted by fb

Area Constraints in Xilinx

Hi, I've been working on an FPGA project for a month or so now and I have finally finished the code. Before I began I c...
8 comments posted 19yrs
posted by ian.peikon
8 comments posted 19yrs posted by ian.peikon

I look for a wideband SERDES chip

Hello I have got a problem in SERDES chip selection that I would be grateful if someone helps me in this regard. First,...
5 comments posted 19yrs
posted by arash.majd
5 comments posted 19yrs posted by arash.majd

Stratix-III announced

S-III L == V5LX S-III E == V5SX S-III GX == V5xxT 1000-unit pricing starts at $549 for the EP3SL150 Quartus WebPack supp...
19 comments posted 19yrs
posted by Antti.Lukats
19 comments posted 19yrs posted by Antti.Lukats

opb_ddr

Hi all, I have problems with runnig a DDR test on Spartan3E SK. I rebuild one of the reference designs in EDK 8.2: http...
1 comments posted 19yrs
posted by ales.gorkic
1 comments posted 19yrs posted by ales.gorkic

Why 64-bit PLB?

Can anyone tell me why the default width for the PLB in EDK is 64-bits when the PPC is a 32-bit processor? I have nothi...
9 comments posted 19yrs
posted by someone
9 comments posted 19yrs posted by someone