simulating two-dimensional array in vhdl

Hello all,

I am trying to use a two-dimensional array in the port of a vhdl program as follows:

entity tree_adder is port ( A : in inhibitory_weights_array; S : out std_logic_vector(15 downto 0) ); end tree_adder;

where inhibitory_weights_array is defined in a package as:

TYPE inhibitory_weights_array IS array(0 to 23) of std_logic_vector(15 downto 0);

Synthesis do not show any error, but when I try to check his behavioral simulation, the following error happen:

The testbench tool fails to create the right waveform, making port A as an array of 24 elements of bit (equivalent to std_logic_vector(23 downto 0).

I have tried several options for example I changed the entity to:

entity tree_adder is port ( A0 : in std_logic_vector(15 downto 0); A1 : in std_logic_vector(15 downto 0); . . . . . . . . . . . . A23 : in std_logic_vector(15 downto 0); S : out std_logic_vector(15 downto 0) ); end tree_adder;

and then defining a signal (after architecture)

signal B : inhibitory_weights_array;

begin B(0)

Reply to
ruben.gue
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Consider posting the testbench code to comp.lang.vhdl

-- Mike Treseler

Reply to
Mike Treseler

Ok, I will do it right now, thanks,

Ruben

Reply to
ruben.gue

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