regarding changing serial data out to LVDS form

All voltage standards (like LVDS) are specified as user constraints. Consult the Spartan or ISE documentation for the precise details

KJ

Give us a clue here. Are you working in VHDL or Verilog? Xilinx, Altera, or other? Most systems that support LVDS have a technology dependent component that will support LVDS transmissions. Unless we know what you are working with, we can't help.

Brad Smallridge aivision

Oops. Belay that last message. I'm not reading well this morning.

Here are some code snips from my Virtex4 platform which should be about the same for your Spartan3s:

top level VHDL:

my_serial_to_cam2_OBUFDS : OBUFDS port map ( O => cam2_serial_out_p, -- to cam2 OB => cam2_serial_out_n, -- to cam2 I => serial_to_cam2 );

serial_from_cam2_IBUFDS : IBUFDS port map ( O => serial_from_cam2, I => cam2_serial_in_p, -- from cam2 IB => cam2_serial_in_n ); -- from cam2

Underneath the top level I have a code module that deals with only non-differential signals. I never did find out a way to simulate differential signals.

In your UCF file:

# Serial Port from and to CAM2 NET "cam2_serial_out_n" LOC = AF22; # HDR2_42 NET "cam2_serial_out_p" LOC = AF21; # HDR2_44 NET "cam2_serial_in_n" LOC = AF20; # HDR2_30 NET "cam2_serial_in_p" LOC = AF19; # HDR2_32 # differential termination applied to input IBUFD INST serial_from_cam2_IBUFDS DIFF_TERM = TRUE; # must match top

Hope this helps.

Brad Smallridge aivision

And another oops. INST my_serial_from_cam2_IBUFDS DIFF_TERM = TRUE; # must match top Brad