Power-on reset

Xilinx comes up in a programmable known state. You can instantiate the ROC primitive to make your design take advantage of it (unless explicitly told otherwise, all the flip-flops come up cleared).

Thanks Ray,

but

I was perhaps a bit unclear. The power-on-reset is something I will need for synthesis. I wonder if the Xilinx part has a power-on detection circuit with a logical output that I could OR with my (active high) reset input.

I don't mind the gates resetting to '0', but I'm using some random number generators that have constant, nonzero seeds set up in my code.

Regards, B=F8rge

Ray Andraka wrote

Actually, any FDP, FDPE, FDS, or FDSE primitives come up set unless explicitly told otherwise, at least in the Spartan-N(E) families I've used. The FD, FDR, FDRS, FDC, FDCP, FDE, FDRE, FDRSE, FDCE, and FDCPE primitives all come up cleared as expected unless explicitly told otherwise.

All BlockRAM and CLB SelectRAM (including SRLs) come up cleared by default but can be overridden as well.

As all the FPGA's FF's are reset to zero on powerup, why not create a counter that inhibits itself after reaching a suitable a preset value when clocked with one of your system clocks? Use the terminal count decode as your POR (adjusting polarity as appropriate).

Slurp

Good idea!

Or perhaps even better, have a register with no reset value be counted up towards a preset and let the local reset be active between preset one and preset two. After reaching preset two there's no more counting.

If we can KNOW that the register is reset to either 0xFF or 0x00, and not the preset values, this should generate a local reset pulse.

So, for example, a 4-bit register could count up from 0 (or F) to 2, activate reset, count to 4 and then deactivate reset and stop counting.

I love your abbreviations, but how would you declare the 4-bit register in practical, synthesizable Verilog?

Thanks, Borge

Slurp skrev:> As all the FPGA's FF's are reset to zero on powerup, why not create a

Yes, that is true if you instantiate the primitives. The synthesis, however, does not force the use of those primitives necessarily. If you want it to come up in a known state then you need to use the ROC.

Borge, yes and no on the ROC. It is there mainly for the benefit of simulation, however if you instantiate the ROC component as a black box, synthesis leaves it in, and the Xilinx translate takes the black boxes out, leaving you with flip-flops that are explicitly forced to a specific starting state.

Synthesis doesn't force the use of the set-on-power-up primitives but it doesn't exclude their use either. Look at any synthesis-produced instance of the mentioned primitives in your designs and you should find they power up to a logic high unless you explicitly override their operation.

Without trying to write verilog after a couple of glasses of wine, use the 'initial' keyword for a block instead of 'always'; it gets executed precisely once (immediately post configuration).

Cheers

PeteS