Is there a dedicated power-on reset function in Verilog? What I want to achieve is that my own reset functionality will be executed when the FPGA (Xilinx Spartan3/400) undergoes power-on reset.
Maybe power-on reset is available as a Xilix core, but I haven't been able to find anything like that.
I was hoping to avoid external POR circuitry.
P.S. Cross-posted to comp.lang.verilog